US 5,854,561 A · Switched substrate bias for MOS DRAM circuits

Abstract

A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

Claims26

Dependent claims

A semiconductor device comprising:

an FET having a source, a drain, and a backgate between said source and said drain;
a level shift circuit including a first transistor responsive to a control signal and coupled between a power supply node and a first node, a second transistor coupled between said first node and a first backgate potential supply node and having a gate coupled to a second node, and a third transistor coupled between said second node and said first backgate potential supply node and having a gate coupled to said first node;
and
a switch circuit including a fourth transistor responsive to a potential of said first node and coupled between said backgate of said FET and said first backgate potential supply node, and a fifth transistor responsive to the potential of said first node and coupled between said backgate of said FET and a second backgate potential supply node.

1 more element

A semiconductor device comprising:

a first pMOS-FET having a source coupled to a first power supply line supplying a power source potential, a drain coupled to a first node, a gate coupled to a second node, and a backgate;
a first nMOS-FET having a source coupled to a second power supply line supplying a ground potential, a drain coupled to said first node, a gate coupled to said second node, and a backgate coupled to said second power supply line;
a second pMOS-FET having a source coupled Lo said first power supply line, a drain coupled to a third node, a gate coupled to said first node, a backdate coupled to said first power supply line;
a second nMOS-FET having a source coupled to said second power supply line, a drain coupled to said third node, a gate coupled to said first node, a backgate;
a first switch circuit coupled to said backgate of said first pMOS-FET, a first backgate potential supply node, and a second backgate potential supply node;
and
a second switch circuit coupled to said backgate of said second nMOS-FET, a third backgate potential supply node, and a fourth backgate potential supply node.

4 more elements

A semiconductor device comprising:

a first pMOS-FET having a source coupled to a first power supply line supplying a power source potential, a drain coupled to a first node, a gate coupled to a second node, and a backgate coupled to said first power supply line;
a first nMOS-FET having a source coupled to a second power supply line supplying a ground potential, a drain coupled to said first node, a gate coupled to said second node, and a backgate;
a second pMOS-FET having a source coupled to said first power supply line, a drain coupled to a third node, a gate coupled to said first node, and a backgate;
a second nMOS-FET having a source coupled to said second power supply line, a drain coupled to said third node, a gate coupled to said first node, and a backgate coupled to said second power supply line;
a first switch circuit coupled to said backgate of said second pMOS-FET, a first backgate potential supply node, and a second backgate potential supply node;
and
a second switch circuit coupled to said backgate of said first nMOS-FET, a third backgate potential supply node, and a fourth backgate potential supply node.

4 more elements

A semiconductor device comprising:

a first pMOS-FET coupled between a primary power supply line and a secondary power supply line, and responsive to a control signal;
a first nMOS-FET coupled between a primary ground line and a secondary ground line, and responsive to a complementary signal of said control signal;
a second pMOS-FET coupled between said secondary power supply line and a first node, and having a gate coupled to a second node;
a second nMOS-FET coupled between said secondary ground line and said first node, and having a gate coupled to said second node;
a third pMOS-FET coupled between said secondary power supply line and a third node, and having a gate coupled to said first node;
a third nMOS-FET coupled between said secondary ground line and said third node, and having a gate coupled to said first node;
a first switch circuit coupled to a backgate of said third pMOS-FET, a first backgate potential supply node, and a second backgate potential supply node;
and
a second switch circuit coupled to said backgate of said second nMOS-FET, a third backgate potential supply node, and a fourth backgate potential supply node.

6 more elements

Dependencies are inferred from the claim text.

Switched substrate bias for MOS DRAM circuits

Life of this patent

Switched substrate bias for MOS DRAM circuits

Life of this patent

Abstract

Claims26