CMOS output buffer having a high current driving capability with low noise

An tri-state output buffer, comprising:

• a first driver, comprising a plurality of pull-up CMOS transistors, each separated by a respective resistor, for driving a terminal to a voltage corresponding to a high logic value of a first output signal, said plurality of pull-up transistors activate sequentially with an R-C delay from said respective resistor when the output from said second predriver is low;
• a second driver, comprising a plurality of Pull-down CMOS transistors, each separated by a respective resistor, for driving said terminal to a voltage corresponding to a low logic value of a second output signal, said plurality of pull-down transistors activate sequentially with an R-C delay from said respective resistor when the output from said first predriver is high;
• a first predriver circuit comprising a first logic gate having an output connected to said first driver and an input connected to an enable signal and to the output of a second logic gate, said second logic gate having an input connected to an inverted first or second output signal and to a second control signal;
• and
• a second predriver circuit comprising a third logic gate having an output connected to said second driver and an input connected to the inverted enable signal and to the output of a fourth logic gate, said fourth logic gate having an input connected to said inverted first or second output signal and to a first control signal,
• wherein said first control signal represents a delayed output of said first logic gate, and said second control signal represents a delayed output of said third logic gate, and wherein said delayed output of said first and second logic gates being delayed by said R-C delay.

An integrated circuit, comprising:

• a terminal;
• a first plurality of driver transistors for driving said terminal to a voltage corresponding to a high logic value of a first output signal;
• a second plurality of driver transistors for driving said terminal to a voltage corresponding to a low logic value of a second output signal;
• a first predriver circuit having an output connected to the first said transistor in said first plurality of driver transistors and having an input to receive the complement of said first output signal and a second control signal;
• a second predriver circuit having an output connected to the first said transistor in said second plurality of driver transistors and having an input to receive the complement of said second output signal and a first control signal,
• wherein said first control signal represents a delayed output of said first predriver circuit, and said second control signal represents a delayed output of said second delayed output circuit;
• a first plurality of logic gates, each connected in series between two sequential transistors in said first plurality of driver transistors, having an output connected to the gate of the respective transistor, wherein the first logic gate of said first plurality of logic gates has an input to receive said complement of said first output signal and said first control signal;
• and
• a second plurality of logic gates, each connected in series between two sequential transistors in said second plurality of driver transistors, having an output connected to the gate of the respective transistor, wherein the second logic gate of said second plurality of logic gates has an input to receive said complement of said second output signal and said second control signal.