US 5,854,497 A · Semiconductor memory device

Abstract

A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

A semiconductor memory device comprising:

pairs of first and second memory cells each having transistor regions arranged in a first direction, wherein said first memory cell is arranged adjacent to said second memory cell in a second direction perpendicular to said first direction,
each of said first and said second memory cells comprising a pair of n channel MISFETS, a pair of p channel MISFETs, and a first and a second interconnect line such that gate electrodes of said n channel MISFETs and said p channel MISFETs overlie a main surface of a semiconductor substrate, such that source and drain regions of said n channel MISFETs and said p channel MISFETs are formed in said substrate, such that first interconnect line is electrically connected between said drain region of one of said pair of said n channel MISFETs and said drain region of one of said pair of said p channel MISFETs, and such that said second interconnect line is electrically connected between said drain region of the other of said pair of said n channel MISFETs and said drain region of the other of said pair of said p channel MISFETs,
a first conductive layer overlying said main surface and formed of the same level layer as said first and said second interconnect lines,
wherein, in said pair of said first and said second memory cells, said p channel MISFETs of said first and said second memory cells are arranged, in said second direction, between said n channel MISFETs of said first memory cell and said n channel MISFETs of said second memory cell,
wherein, in said pair of said first and second memory cells, said first conductive layer is electrically connected to said source regions of said p channel MISFETs of said first memory cell and to said source regions of said p channel MISFETs of said second memory cell,
wherein, in said pair of said first and said second memory cells, said first interconnect line of said first memory cell is arranged, in said second direction, adjacent to said first interconnect line of said second memory cell such that no conductive layer, including said first conductive layer, formed of the same level layer as said first and said second interconnect lines is positioned, in said second direction, between said first interconnect line of said first memory cell and said first interconnect line of said second memory cell,
wherein, in said pair of said first and said second memory cells, said second interconnect line of said first memory cell is arranged, in said second direction, adjacent to said second interconnect line of said second memory cell such that the first conductive layer formed of the same level layer as said first and said second interconnect line is not positioned, in said second direction, between said first interconnect line of said first memory cell and said first interconnect line of said second memory cell,
wherein said first and said second interconnect lines are spaced apart from said first conductive layer in said first direction;
and
a wiring line extending in said first direction and formed of a different level layer than said first conductive layer and than said first and second interconnect lines,
wherein said wiring line is electrically connected to said source regions of said p channel MISFETs of said first and second memory cells through said first conductive layer.

8 more elements

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims17