Dummy fill patterns to improve interconnect planarity

In the manufacture of integrated circuits, a method of processing a semiconductor wafer having at least one integrated circuit, the method comprising the steps of:

• forming a multiplicity of active conductive traces on a substrate of the wafer, the active conductive traces being arranged to electrically couple associated elements of an associated integrated circuit on the wafer, there being gaps exceeding a threshold distance between at least some adjacent ones of the traces, wherein the threshold distance is greater than approximately 2 micrometers;
• forming a multiplicity of dummy surfaces on the substrate in the gaps, wherein the dummy surfaces are not arranged to electrically couple any elements in the integrated circuit, the dummy surfaces being arranged in a micro-pattern configured to inhibit a flow of a spin-on glass;
• depositing a dielectric layer over the active conductive traces to electrically insulate the active conductive traces;
• spinning a layer of glass over the dielectric layer to provide a planar surface on the wafer, the glass layer being superimposed over the active conductive traces and the dummy surfaces, wherein the dummy surfaces that are arranged in the micro-pattern inhibit the flow of the layer of glass to provide an even coating of the glass layer over the dielectric layer so as to provide the planar surface on the wafer;
• and
• etching the glass layer to expose at least portions of the dielectric layer.

In the manufacture of integrated circuits, a method of processing a semiconductor wafer having at least one integrated circuit, the method comprising the steps of:

• forming a multiplicity of active conductive traces on a substrate of the wafer, the active conductive traces being arranged to electrically couple associated elements of an associated integrated circuit on the wafer, there being gaps exceeding a threshold distance between at least some adjacent ones of the traces;
• forming a multiplicity of dummy surfaces on the substrate in the gaps, wherein the dummy surfaces are not arranged to electrically couple any elements in the integrated circuit, the dummy surfaces being arranged in a micro-pattern configured to inhibit a flow of a spin-on glass, wherein the dummy surfaces comprise a first set of parallel lines and a second set of parallel lines which intersect to form the micro-pattern, the dummy surfaces being line segments;
• depositing a dielectric layer over the active conductive traces to electrically insulate the active conductive traces;
• spinning a layer of glass over the dielectric layer to provide a planar surface on the wafer, the glass layer being superimposed over the active conductive traces and the dummy surfaces, wherein the dummy surfaces that are arranged in the micro-pattern inhibit the flow of the layer of glass to provide an even coating of the glass layer over the dielectric layer so as to provide the planar surface on the wafer;
• and
• etching the glass layer to expose at least portions of the dielectric layer.