Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide

A method for fabricating shallow trench isolation structures for use with non-volatile memory devices to maintain sufficient data retention thereof, comprising the steps of:

• providing a semiconductor substrate;
• forming an epitaxial layer on a top surface of said semiconductor substrate;
• forming a barrier oxide layer on a top surface of said epitaxial layer;
• depositing a nitride layer on a top surface of said barrier oxide layer;
• forming trenches through said epitaxial layer and said barrier oxide layer to a depth greater than 4000 .ANG. below the top surface of said epitaxial layer so as to create isolation regions in order to electrically isolate active regions in said epitaxial layer;
• forming a liner oxide layer on sidewalls and bottom of said trenches to a thickness between 750 .ANG. to 1500 .ANG.;
• filling completely said trenches with a TEOS oxide layer;
• removing said TEOS layer down to the top surface of said nitride layer;
• planarizing said TEOS oxide layer;
• removing said nitride layer;
• and
• forming a non-volatile memory device having a programming junction implant in one of said active regions in said epitaxial layer.