Method for fabricating power transistor using silicon-on-insulator (SOI) wafer

Abstract

An improved method for fabricating a power transistor using an SOI wafer which is capable of using an SOI substrate having a thin Si film, which includes the steps of a first step for forming an SOI layer having a first oxidation film and a single crystal Si thin film by implanting an oxygen ion with respect to a single crystalline substrate and heat-treating the same, a second step for forming source and drain electrodes of a first poly-crystal Si film encircled by a third oxidation film on the SOI substrate, a third step for forming a shallow junction by ion-implanting with respect to the source and drain electrodes of the first poly-crystalline Si film, a fourth step for forming a second poly-crystalline Si film by a reactive ion etching method with respect to the third oxide film so as to form a gate electrode, and a fifth step for stabilizing a voltage at a lower channel portion, which voltage is supplied thereto through a p-type region of the SOI layer, and for ion-implanting a p-type dopant ion using a photoresistive film as a mask so as to supply a voltage to the lower portion of the SOI layer beneath the channel portion, and for forming source and drain electrode.

Dependencies are inferred from the claim text.