US 5,854,102 AGranted

Vertical diode structures with low series resistance

AssigneeMicron Technology, Inc.

InventorsFernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme

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Abstract

A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Claims19

Dependent claims

A method for forming a diode on a silicon wafer, the silicon wafer having an exposed surface and being doped with a first conductivity type dopant, the method comprising the steps of:

(a) highly doping a portion of the exposed surface of the silicon wafer with a second conductivity type dopant to form an active region;
(b) disposing a first refractory metal silicide layer over said active region;
(c) forming a layer of insulation material over said first refractory metal silicide layer;
(d) etching a diode opening through said layer of insulation material to expose a portion of said first refractory metal silicide layer, said diode opening being defined by an interior surface;
(e) filling said diode opening with an amorphous silicon to form a silicon plug, said silicon plug comprising a bottom portion contacting said active region and a top portion separated from said active region by said bottom portion;
(f) lightly doping said amorphous silicon with said second conductivity type of dopant;
(g) heating said amorphous silicon to convert said amorphous silicon to large grain polysilicon;
(h) highly doping said top portion of said silicon plug with said first conductivity type of dopant;
and
(i) securing a metal contact onto said top portion of said silicon plug.

7 more elements

A method for forming a diode on a silicon wafer, the silicon wafer having an exposed surface and being doped with a first conductivity type dopant, the method comprising the steps of:

(a) highly doping a portion of the exposed surface of the silicon wafer with a second conductivity type dopant to form an active region;
(b) disposing a first refractory metal silicide layer over said active region;
(c) forming a layer of insulation material over said first refractory metal silicide layer;
(d) etching a diode opening through said layer of insulation material to expose a portion of said first refractory metal silicide layer, said diode opening being defined by an interior surface;
(e) covering said layer of insulation material and said interior surface of said diode opening with a polysilicon layer;
(f) applying a refractory metal layer over said polysilicon layer;
(g) exposing said refractory metal layer to a temperature sufficient to chemically react said polysilicon layer with said refractory metal layer to form a second refractory metal silicide layer positioned over said layer of insulation material and on said interior surface of said diode opening;
(h) depositing a layer of said amorphous silicon over said refractory metal silicide layer so as to fill said diode opening;
(i) removing said layer of amorphous silicon and said second refractory metal silicide layer overlying said layer of insulation to form a silicon plug within said diode opening, said silicon plug comprising a bottom portion contacting said second refractory metal silicide layer lining said diode opening and a top portion partially bounded by said bottom portion so as to be separated from said second refractory metal silicide layer;
(j) lightly doping said amorphous silicon with said second conductivity type of dopant;
(k) heating said amorphous silicon to convert said amorphous silicon to large grain polysilicon;
(l) implanting a high concentration of ions of said first conductivity type of dopant within said top portion of said silicon plug;
(m) annealing said top portion of said silicon plug having said ions of said first type of dopant implanted therein;
(n) positioning an insulative silicon layer on said layer of insulation and over said diode opening;
(o) etching a passageway through said insulative silicon layer and down to said top portion of said silicon plug;
(p) placing a layer of chalcaginide material over said insulative silicon layer and within said passageway so as to contact said top portion of said silicon plug;
(q) locating a layer of titanium nitride over said chalcaginide material;
and
(r) securing a metal contact onto said layer of titanium nitride.

16 more elements

Dependencies are inferred from the claim text.