Programmable read-write word line equality signal generation for FIFOs
AssigneeCypress Semiconductor Corporation
InventorsAndrew L. Hawkins, Pidugu L. Narayana, Roland T. Knaack
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Abstract
The present invention provides a circuit for generating a programmable write-read word line equality signal in FIFO buffers. The present invention significantly reduces the gate delay associated in producing the write-read word line equality signal. The delay is reduced from a typical 30-50 gate delays, to as little as four gate delays. The present invention accomplishes this by processing several bit operations in parallel and making the general circuit architecture symmetric. The delay is constant in all of the parallel paths but amounts to only a short delay for the final WREQ output.
Claims13
A circuit comprising:
- a FIFO buffer having a plurality of write enable signals, a plurality of read enable signals, a read pointer and a write pointer;
- a first circuit configured to generate an internal signal indicating when said read pointer is within a specified offset of said write pointer in response to (i) a first input coupled to said write pointer, (ii) a second input coupled to said read pointer and (iii) an offset input for receiving said specified offset;
- a logic circuit configured to generate a read write equality signal in response to (i) said internal signal, (ii) said plurality of write enable signals and (iii) said plurality of read enable signals.
Dependencies are inferred from the claim text.