VLIW processor which processes compressed instruction format
AssigneePhilips Electronics North America Corporation
InventorsEino Jacobs, Michael Ang
Life of this patent
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Abstract
A VLIW processor uses a compressed instruction format that allows greater efficiency in use of cache and memory. Instructions are byte aligned and variable length. Branch targets are uncompressed. Format bits specify how many issue slots are used in a following instruction. NOPS are not stored in memory. Individual operations are compressed according to features such as whether they are resultless, guarded, short, zeroary, unary, or binary. Instructions are stored in compressed form in memory and in cache. Instructions are decompressed on the fly after being read out from cache.
Claims27
A VLIW processor for using compressed instructions, the processor comprising
- an instruction issue register comprising a plurality of issue slots, each issue slot being for storing a respective operation, all of the operations starting execution in a same clock cycle;
- a plurality of functional units for executing the operations stored in the instruction register;
- a decompression unit for providing decompressed instructions to the instruction issue register, the decompression unit taking compressed instructions from a compressed instruction storage medium and decompressing the compressed instructions, at least one of the compressed instructions including at least one operation, each operation being compressed according to a compression scheme which assigns a compressed operation length to that operation, the compressed operation length being chosen from a plurality of finite lengths, which finite lengths include at least two non-zero lengths, which of the finite lengths is chosen being dependent upon at least one feature of the operation.
The processor of 9 wherein the format field has 2*N bits, where N is the number of issue slots.
The processor of 10 wherein the at least one field specifying the operation comprises at least one byte aligned sub-field.
A VLIW processor for using compressed instructions, the processor comprising:
- an instruction issue register comprising a plurality of issue slots, each issue slot being for storing a respective operation, all of the operations starting execution in a same clock cycle;
- a plurality of functional units for executing the operations stored in the instruction register;
- a decompression unit for providing decompressed instructions to the instruction issue register, the decompression unit taking a stream of compressed instructions from a compressed instruction storage medium and decompressing the compressed instructions, the stream of instructions comprising:
- at least one first instruction which is a branch target and which is uncompressed;
- and
- at least one second instruction following the branch target which is compressed according to a scheme in which each instruction is assigned a format according to features of that instruction.
A VLIW processor for using compressed instructions, the processor comprising:
- an instruction issue register comprising a plurality of issue slots, each issue slot being for storing a respective operation, all of the operations starting execution in a same clock cycle;
- a plurality of functional units for executing the operations stored in the instruction register;
- a decompression unit for providing decompressed instructions to the instruction issue register, the decompression unit taking a stream of compressed instructions from a compressed instruction storage medium and decompressing the compressed instructions, the stream of instructions comprising:
- a first instruction including
- a format field which specifies an instruction compression format and
- at least one operation field;
- and
- a second instruction, following the first instruction, that is compressed according to the format field in the first instruction.
A processor comprising
- an instruction register;
- at least one functional unit for executing an operation from the instruction register;
- a decompression unit for providing decompressed instructions to the instruction register, the decompression unit taking a stream of compressed instructions from a compressed instruction storage medium and decompressing the compressed instructions, the stream of instructions comprising:
- a first instruction including a first format field which specifies an instruction compression format;
- and
- a second instruction, following the first instruction, the second instruction including a second format field and a compressed operation, the compressed operation being compressed according to the first format field.
A VLIW processor for using compressed instructions, the processor comprising:
- an instruction issue register comprising a plurality of issue slots, each issue slot being for storing a respective operation, all of the operations starting execution in a same clock cycle;
- a plurality of functional units for executing the operations stored in the instruction register;
- a decompression unit for providing decompressed instructions to the instruction issue register, the decompression unit taking a stream of compressed instructions from a compressed instruction storage medium and decompressing the compressed instructions, the instruction stream comprising a stored VLIW instruction, the instruction comprising a plurality of operations for commencing execution in a same machine cycle on distinct functional units of a VLIW processor, each operation having an executable form having a respective executable operation length, each non-null operation being stored on the medium in a respective compressed form according to a compression scheme which assigns a respective compressed operation length to that non-null operation, the compressed operation length being less than the executable operation length.
Dependencies are inferred from the claim text.