Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down

An electronic system comprising:

• a static CMOS component;
• a programmable power supply source coupled to the static CMOS component by a power line, the programmable power source selectively supplying to the static CMOS component an operating voltage and a low voltage substantially lower than the operating voltage but sufficient to maintain register and internal state levels of the static CMOS component;
• and
• a system controller coupled to the programmable power supply by a power control line for selecting the supplied voltage and coupled to the static CMOS component by a status line indicative of component status, the system controller calibrating the low reference voltage pertaining to the static CMOS component in a suboperation included in a system bootstrap operation.

A method of operating a static CMOS component comprising the steps of:

• selectively supplying a reference voltage at a plurality of voltage levels including an operating voltage level and a low reference voltage which is substantially lower than the operating voltage level but sufficient to maintain register and internal state levels of a static CMOS component;
• detecting an idle state of the static CMOS component;
• controlling the selectively supplying step to supply the low reference voltage in response to detection of the idle state;
• maintaining the register and internal state levels of the static CMOS component by supplying the low reference voltage;
• and
• calibrating the low reference voltage pertaining to the static CMOS component in a suboperation included in a system bootstrap operation.

An electronic system comprising:

• a static CMOS component;
• a programmable power supply source coupled to the static CMOS component by a power line, the programmable power source supplying to the static CMOS component a voltage selected from a plurality of voltages including an operating voltage and a low voltage substantially lower than the operating voltage but sufficient to maintain register and internal state levels of a static CMOS component;
• and
• a system controller coupled to the programmable power supply by a power control line for selecting the supplied voltage and coupled to the static CMOS component by a status line indicative of component status including an active status and an idle status, the system controller including:
• a control logic responsive to the idle status signal on the status line by selecting the low voltage substantially lower than the operating voltage but sufficient to maintain register and internal state levels of the static CMOS component, the control logic calibrating the low reference voltage pertaining to the static CMOS component in a suboperation included in a system bootstrap operation.

A method of operating a static CMOS processor comprising the steps of:

• selectively supplying a reference voltage at a plurality of voltage levels including an operating voltage level and a low reference voltage which is substantially lower than the operating voltage level but sufficient to maintain register and internal state levels of a static CMOS processor;
• detecting an idle state of the static CMOS processor;
• controlling the selectively supplying step to supply the low reference voltage in response to detection of the idle state;
• maintaining the register and internal state levels of the static CMOS processor by supplying of the low reference voltage;
• and
• calibrating the low reference voltage pertaining to the static CMOS processor in a suboperation included in a system bootstrap operation.

An electronic system comprising:

• a static CMOS processor;
• a programmable power supply source coupled to the static CMOS processor by a power line, the programmable power source supplying to the static CMOS processor a voltage selected from a plurality of voltages including an operating voltage and a low voltage substantially lower than the operating voltage but sufficient to maintain register and internal state levels of a static CMOS processor;
• and
• a system controller coupled to the programmable power supply by a power control line for selecting the supplied voltage and coupled to the static CMOS processor by a status line indicative of processor status including an active status and an idle status, the system controller including:
• a control logic responsive to an idle status signal on the status line by selecting the low voltage substantially lower than the operating voltage but sufficient to maintain register and internal state levels of the static CMOS processor, the control logic calibrating the low reference voltage pertaining to the static CMOS component in a suboperation included in a system bootstrap operation.