US 5,852,727 AGranted

Instruction scanning unit for locating instructions via parallel scanning of start and end byte information

AssigneeAdvanced Micro Devices, Inc.

InventorsRammohan Narayan, Thang M. Tran

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Abstract

An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

Claims20

Dependent claims

An instruction scanning unit for scanning a block of predecode information associated with a plurality of contiguous instruction bytes wherein said block of predecode information includes start byte information indicative of bytes which start instructions and wherein said block of predecode information further includes end byte information indicative of bytes which end instructions, said instruction scanning unit comprising:

a first subunit coupled to receive said start byte information, and wherein said first subunit is configured to generate a plurality of instruction valid values, and wherein each of said plurality of instruction valid values is indicative of a potential valid instruction starting at a first byte within said plurality of contiguous instruction bytes and ending at a second byte within said plurality of contiguous instruction bytes, and wherein said first byte is indicated to be a start byte by said start byte information, and wherein said second byte is different for each one of said plurality of instruction valid values;
and
a second subunit coupled to receive said end byte information, and wherein said second subunit is configured to generate a plurality of instruction end counts, and wherein each of said instruction end counts is indicative of a number of instructions which end between a first one of said plurality of contiguous instruction bytes and a particular one of said plurality of contiguous instruction bytes, and wherein said first subunit and said second subunit operate in parallel.

A method for concurrently locating variable byte length instructions, comprising:

scanning start byte information corresponding to a plurality of contiguous bytes to create a plurality of instruction valid values, wherein each of said plurality of instruction valid values is indicative of a potential valid instruction beginning at a first of said plurality of contiguous bytes and ending at a second of said plurality of contiguous bytes, and wherein said first of said plurality of contiguous bytes is identified by said start byte information to be a start byte;
and
selecting one of said plurality of instruction valid values, wherein said second one of said plurality of contiguous bytes corresponding to said one of said plurality of instruction valid values is identified by end byte information corresponding to said plurality of instruction valid values to be an end byte.

A microprocessor comprising:

an instruction cache configured to store instruction bytes and corresponding predecode data including start byte information indicative of which instruction bytes are start bytes of instructions and end byte information indicative of which instruction bytes are end bytes of instructions;
and
an instruction scanning unit coupled to receive said instruction bytes and said corresponding predecode data from said instruction cache, wherein said instruction scanning unit is configured to scan said start byte information to identify potential valid instructions, each potential valid instruction beginning at a first byte indicated by said start byte information to be a start byte and ending at a second byte which differs for each potential valid instruction, and wherein said instruction scanning unit is configured to scan said end byte information in parallel to generate an end count corresponding to each instruction byte, and wherein said instruction scanning unit is configured to identify a plurality of instructions from said potential valid instructions using said end counts.

Dependencies are inferred from the claim text.