Microprocessor having single poly-silicon EPROM memory for programmably controlling optional features

A microprocessor comprising:

• a microprocessor core;
• an electrically programmable non-volatile memory coupled for write access by said microprocessor core and having an address interface and a data interface, the address interface being coupled to receive an address from said microprocessor core;
• a circuit coupled to receive one or more control signals from the data interface of said memory, the state of the one or more control signals being determined by a control value stored in said memory at the address received from said microprocessor core;
• and
• wherein said circuit is a pin-out control circuit configured to define one of a plurality of different pin-out interfaces for said microprocessor based on the state of the one or more control signals.

A microprocessor comprising:

• a microprocessor core;
• an electrically programmable non-volatile memory coupled for write access by said microprocessor core and having an address interface and a data interface, the address interface being coupled to receive an address from said microprocessor core;
• a circuit coupled to receive one or more control signals from the data interface of said memory, the state of the one or more control signals being determined by a control value stored in said memory at the address received from said microprocessor core;
• a floating point processor;
• and
• wherein said circuit is a control circuit configured to either enable or disable said floating point processor based on the state of the one or more control signals.

A microprocessor comprising:

• a microprocessor core;
• an electrically programmable non-volatile memory coupled for write access by said microprocessor core and having an address interface and a data interface, the address interface being coupled to receive an address from said microprocessor core;
• a circuit coupled to receive one or more control signals from the data interface of said memory, the state of the one or more control signals being determined by a control value stored in said memory at the address received from said microprocessor core;
• and
• wherein said circuit is a control circuit configured to establish an operating frequency for said microprocessor based on the state of the one or more control signals.

A microprocessor comprising:

• a microprocessor core;
• an electrically programmable non-volatile memory coupled for write access by said microprocessor core and having an address interface and a data interface, the address interface being coupled to receive an address from said microprocessor core;
• a circuit coupled to receive one or more control signals from the data interface of said memory, the state of the one or more control signals being determined by a control value stored in said memory at the address received from said microprocessor core;
• and
• wherein said circuit is a control circuit configured to trim the output of a component in said microprocessor based on the state of the one or more control signals.

A microprocessor comprising:

• a microprocessor core;
• a cache memory coupled to said microprocessor core;
• an electrically programmable non-volatile memory coupled for write access by said microprocessor core and having an address interface and a data interface, the address interface being coupled to receive an address from said microprocessor core;
• a circuit coupled to receive one or more control signals from the data interface of said non-volatile memory, the state of the one or more control signals being determined by a control value stored in said non-volatile memory at the address received from said microprocessor core;
• and
• wherein said circuit is a cache repair unit to remap an address to a defective storage element in said cache memory to address a storage element indicated by the one or more control signals.