Simplified architecture for defuzzification integrated circuit (IC) processor including circuits for estimating effective areas without overlapping errors

A fuzzy logic control system, including a defuzzification section, for generating a crisp output from a plurality of fuzzy logic signals defining membership functions generated by the fuzzy logic control system, the defuzzification section comprising:

• effective area computing means for computing an effective area for each of said membership functions, said effective area computing means including a multi-overlapping effective area computing means for computing an effective area for said membership functions when the membership functions overlap multiple times;
• said multi-overlapping effective area computing means further including an overlapping number computing means for computing an overlapping number for said overlapping areas for each of said membership functions;
• specific weight computing means for computing a specific weight of each of said membership functions;
• an input port for receiving input values .alpha., said specific weight and said effective area for each of said membership functions;
• multiplication-and-adding means for computing a first sum of the input values and said specific weights of corresponding membership functions and a second sum of the products of the input values to said effective area of corresponding membership functions;
• dividing means for dividing said first sum by said second sum to obtain a crisp output of said membership functions of the fuzzy control logic system;
• and
• means for providing the crisp output to external logic.

A defuzzification process for generating a crisp output from a plurality of fuzzy logic membership functions, comprising the steps of:

• (a) receiving an input value .alpha., a specific weight, and an effective area for each of said membership functions;
• (b) computing a first sum of the products of said input value .alpha. and said specific weight of corresponding membership functions and a second sum of the products of said input value .alpha. and said effective area of corresponding membership functions;
• (c) dividing said first sum by said second sum to obtain said crisp output of said membership functions;
• and
• (d) transmitting the crisp output to non-fuzzy logic circuitry.

A circuit device for computing a centroid of integrated polygons of a plurality of .alpha.-Dot polygons having a plurality of intersected areas, comprising:

• an input port for receiving a plurality of input values for said .alpha.-Dot operation, and a specific weight and an effective area for each of said .alpha.-Dot polygons;
• multiplication-and-adding means for computing a first sum of the products of said input values and said specific weight and a second sum of the products of said input values and said effective area;
• dividing means for dividing said first sum by said second sum to obtain said centroid of said integrated polygons;
• and
• means for providing the centroid to external logic.