Clock distribution apparatus with current sensed skew cancelling
OwnerPhillip S. Kliza, William P. Corneliusinventors
Life of this patent
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Abstract
A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses traces configured as reflective transmission lines with a matched impedance input. The propagation time of a transmission line is determined by monitoring the current into the transmission line. Variable delays are determined for each transmission line by measuring the actual propagation time and reducing a predetermined maximum delay time by that amount. The variable delay values are stored and used to retard clock edges by the varying amounts so that all clock edges arrive at respective remote destinations at a time equal to the maximum delay time.
Claims23
A clock distribution circuit for achieving substantially simultaneous arrival of timing events at a plurality of digital subsystems comprising:
- a clocking means for generating said timing events, said clocking means having a plurality of outputs, each of said outputs being effective for supplying a copy of said timing events;
- a plurality of transmission lines;
- a plurality of current sensing means;
- a plurality of delay means;
- each of said plurality of digital subsystems being coupled to said clock distribution circuit at only a corresponding one of said plurality of outputs, each of said plurality of digital subsystems being coupled to said corresponding one of said outputs via a single one of said transmission lines whereby each of said digital subsystems receives one of said conies of said timing events;
- each of said plurality of current sensing means being coupled to a corresponding one of said plurality of transmission lines, each of said current sensing means being effective for determining a current flow time during which current flows in said corresponding one of said transmission lines;
- each of said plurality of transmission lines being coupled to a corresponding one of said plurality of delay means, each of said plurality of delay means being effective for delaying said timing events by an amount dependent on a predetermined maximum delay reduced by one-half said current flow time whereby the propagation delay of said timing events from each of said outputs to its corresponding one of said digital subsystems is equalized to said predetermined maximum delay.
A clock distribution circuit for achieving simultaneous arrival of clock timing events at digital subsystems comprising:
- a source of said clock timing events having a plurality of output points, each of said plurality of output points being connected to a distribution network, said distribution network consisting of a plurality of transmission lines having different lengths;
- each of said digital subsystems receiving said clock timing events via a variable delay element connected by means of one of said transmission lines, said transmission lines being terminated at said digital subsystems with an impedance at least partially reflective of said clock timing events, each of said digital subsystems being coupled to said clock distribution circuit at only one of said output points via one of said transmission lines;
- a plurality of current sensing means for sensing a flow of current in each of said transmission lines;
- a plurality of time measuring means for determining a current flow time during which current flows in each of said transmission lines as determined by said plurality of current sensing means, said current flow time being the propagation time of said clock timing events through each of said transmission lines from said clock distribution circuit to said digital subsystems and back;
- and
- an arithmetic unit means coupled to each time measuring means for determining one-half said current flow time and subtracting said one-half current flow time from a predetermined maximum time, the resultant value being a variable delay signal coupled to a corresponding one of said variable delay elements, each of said variable delay elements being coupled to one of said plurality of transmission lines and effective for delaying said clock timing events by an amount determined by said variable delay signal.
A clock distribution circuit for supplying clock timing events to a digital subsystem and for achieving a clock delay time of said clock timing events substantially similar to a predetermined maximum delay, said clock distribution circuit comprising:
- a source of said clock timing events connected to a variable delay element, said variable delay element being coupled to an output lead;
- a transmission line for coupling said output lead to said digital subsystem;
- said digital subsystem receiving said clock timing events through said variable delay elements, output lead and said transmission line, said transmission line being terminated at said digital subsystem with an impedance at least partially reflective of said clock timing events and effective for producing a reflection signal along said transmission from said digital subsystem to said output lead;
- a current monitoring means coupled to monitor current through said output lead;
- a time measuring means coupled to said current monitoring means and effective for determining a measure of time substantially similar to one-half the time during which current flows through said output lead, this measure of time being similar to a forward propagation time during which a clock timing event propagates from said output lead to said digital subsystem;
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- a servo means responsive to said time measuring means and coupled to monitor a variable delay through said variable delay element, said servo means being effective for servo control of said variable delay element and for adjusting said variable delay element such that the sum of said variable delay through said variable delay element plus said forward propagation time substantially equals said maximum delay time.
Dependencies are inferred from the claim text.