Resynchronization apparatus for error correction code decoder
AssigneeMurata Kikai Kabushiki Kaisha
InventorYasuyuki Murakami
Life of this patent
Estimating the term…
Abstract
An error correction code is a code of n+1 bits which is obtained by applying a predetermined calculation onto data of n bits and attaching a redundant bit, for example. The error correction code can correct errors generated by itself during transmission. However, when "step out" from n+1 bits interval or asynchronous state occurs, the error correction code becomes unable to correct errors. This invention detects the "step out" of the error correction code using a syndrome, carries out a bit shifting on the data and restores synchronization to the error correction code. When data series are continually transmitted as for facsimile image signals, the resynchronization apparatus of this invention is effective.
Claims5
A resynchronization apparatus for an error correction code decoder comprising:
- bit shift means for bit shifting a series of incoming data;
- decoding means for receiving an output of the bit shift means, decoding an error correction code and outputting a syndrome;
- detection means for detecting a bit generation rate of the syndrome;
- and
- control means for making the bit shift means bit shift based on the output of the detection means, wherein the detection means includes a shift register that enters the syndrome and weight count means for counting "1" bit in each stage of the shift register, and the control means causes the bit shifting by the bit shift means when an output of the weight count means reaches above a predetermined value.
Dependencies are inferred from the claim text.