Single-chip synchronous dynamic random access memory (DRAM) system including first address generator operable in first and second modes
AssigneeNEC Corporation
InventorMamoru Fujita
Life of this patent
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Abstract
To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially.
Claims20
A synchronous dynamic random access memory (DRAM) system, comprising:
- first and second DRAM cell arrays;
- and
- a first address generator for outputting a first address and a second address respectively to said first and second DRAM cell arrays simultaneously in a first mode, and for outputting said first address and said second address respectively to said first and second DRAM cell arrays sequentially in a second mode,
- said first mode and said second mode depending upon a type of central processing unit (CPU) being provided externally to said DRAM system for operating said DRAM system.
A synchronous dynamic random access memory (DRAM) system, comprising:
- first and second DRAM cell arrays;
- and
- a first address generator for outputting a first address and a second address respectively to said first and second DRAM cell arrays simultaneously in a first mode, and for outputting said first address and said second address respectively to said first and second DRAM cell arrays sequentially in a second mode;
- and
- a second address generator for receiving a third address and a clock signal, for generating a next address of said third address when said clock signal is received in said second mode and outputting said next address, and for generating a fourth address having a difference of a first predetermined number between said third address and said fourth address when said first predetermined number of said clock signal is received in said first mode and outputting said fourth address,
- wherein said first address generator generates said first address and said second address based on said output of said second address generator.
A synchronous dynamic random access memory (DRAM) system, comprising:
- first and second DRAM cell arrays;
- and
- an address generator for outputting a first address and a second address respectively to said first and second DRAM cell arrays simultaneously in a first mode, and for outputting said first address and said second address respectively to said first and second DRAM cell arrays sequentially in a second mode,
- said first mode and said second mode depending upon a type of central processing unit (CPU) being provided externally to said DRAM system for operating said DRAM system,
- wherein said system is formed on a single semiconductor chip.
A decoder for a synchronous dynamic random access memory (DRAM) system, comprising:
- a first address generator for outputting a first address and a second address simultaneously in a first mode, and for outputting said first address and said second address sequentially in a second mode,
- said first mode and said second mode depending upon a type of central processing unit (CPU) being provided externally to said DRAM system for operating said DRAM system.
A decoder, comprising:
- a first address generator for outputting a first address and a second address simultaneously in a first mode, and for outputting said first address and said second address sequentially in a second mode;
- and
- a second address generator for receiving a third address and a clock signal, for generating a next address of said third address when said clock signal is received in said second mode and outputting said next address, and for generating a fourth address having a difference of a first predetermined number between said third address and said fourth address when said first predetermined number of said clock signal is received in said first mode and outputting said fourth address,
- wherein said first address generator generates said first address and said second address by using said output of said second address generator.
Dependencies are inferred from the claim text.