Addressing unit
AssigneeNippon Steel Corporation
InventorAtsuo Koshizuka
Life of this patent
Estimating the term…
Abstract
In an addressing unit fort reducing a wasteful time created to reach an address latch to attain fast processing, a pre-decoder for pre-decoding an X address and a Y address is provided in a preceding stage to the address latch, the address signal pre-decoded by the pre-decoder is latched in the address latch and the latched address signal is decoded by a decoder. Thus, the pre-decode process can be conducted in the same time period required to latch the address signal in a conventional unit in which the pre-decoder is arranged in a succeeding stage of the address latch circuit, and after the address latching, only the decode process is needed.
Claims4
An addressing unit comprising:
- a pre-decoder for sequentially receiving a first address signal and a second address signal, and for sequentially pre-decoding a plurality of address data included in the first address signal and pre-decoding a first one of a plurality of address data included in the second address signal;
- an address latch circuit for latching said plurality of address data included in the pre-decoded first address signal;
- a burst counter for latching the first one of said plurality of address data included in the pre-decoded second address signal and sequentially shifting the latched address data to generate a plurality of address data;
- a control signal generating circuit for generating a first control signal for controlling timing to latch the pre-decoded first address signal and a second control signal for controlling timing to latch the pre-decoded second address signal, and for supplying the first and second control signals to said address latch circuit and said burst counter respectively;
- a first address decoder for decoding said plurality of address data output from said address latch circuit;
- and
- a second address decoder for decoding said plurality of address data generated by said burst counter.
An addressing unit comprising:
- an address buffer for receiving a multiplexed address signal of a first address signal and a second address signal to generate a first internal address signal from the first address signal and generate a second internal address signal from the second address signal;
- a pre-decoder for sequentially receiving the first address signal and the second address signal, and for sequentially pre-decoding a plurality of address data included in the first internal address signal and pre-decoding a first one of a plurality of address data included in the second internal address signal;
- an address latch circuit for latching said plurality of address data included in the pre-coded first internal address signal;
- a burst counter for latching the first one of said plurality of address data included in the pre-decoded second internal address signal and sequentially shifting the latched address data to generate a plurality of address data;
- a control signal generating circuit for generating a first control signal for controlling timing to latch the address data included in the pre-decoded first internal address signal and a second control signal for controlling timing to latch the address data included in the pre-decoded second internal address signal, and for supplying the first and second control signals to said address latch circuit and said burst counter respectively;
- a first address decoder for decoding said plurality of address data output from said address latch circuit;
- and
- a second address decoder for decoding said plurality of address data generated by said burst counter.
Dependencies are inferred from the claim text.