Method of stress testing memory integrated circuits

A method of stress testing a memory integrated circuit die, the method comprising:

• supplying a burn-in power supply voltage and a ground voltage to each memory die of a plurality of memory die on a semiconductor wafer;
• providing the burn-in power supply voltage to a cell plate common node of a memory cell storage capacitor;
• providing the ground voltage to at least one bit line of a plurality of bit lines;
• turning on a cell access transistor between the bit line and a storage node of the memory cell storage capacitor, thereby allowing conduction between the bit line and the storage node of the memory cell storage capacitor, wherein turning on the cell access transistor comprises turning on a particular word line of a plurality of word lines, and wherein the particular word line controls a plurality of cell access transistors and turns on each cell access transistor of the plurality of cell access transistors controlled by the particular word line in response to a voltage applied to the particular word line, wherein the plurality of word lines are arranged in a word line sequence and wherein the turning on of the particular word line comprises turning on alternating word lines in the word line sequence;
• providing the ground voltage to the common cell plate of the memory cell storage capacitor;
• and
• providing the burn-in power supply voltage to at least one bit line of the plurality of bit lines.

A method of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the method comprising:

• providing a burn-in voltage differential between a pair of adjacent word lines in the sequence of word lines to stress insulation between the adjacent word lines;
• reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the adjacent word lines;
• providing the burn-in voltage differential across the common node and the storage node of one of the memory cells to stress insulation between the common node and the storage node;
• reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the common node and the storage node;
• providing the burn-in voltage differential across one of the bit lines and one of the word lines to stress insulation between the one bit line and the one word line;
• and
• reversing polarity of the burn-in voltage differential one or more times to further stress insulation between the one bit line and the one word line.

A method of stressing insulation in a memory integrated circuit die on a wafer, the memory integrated circuit die including a plurality of memory cells, a plurality of bit lines, a sequence of word lines, and a common node, with each memory cell coupled to one of the bit lines, to one of the word lines, and to the common node, the method comprising:

• detecting a predetermined number of cycles of a clock signal;
• providing a burn-in voltage differential across a pair of adjacent word lines in the word line sequence, across the common node and the storage node of one of the memory cells, or across one bit line and one word line, after detecting the predetermined number of cycles of the clock signal;
• and
• reversing polarity of the burn-in voltage differential one or more times.