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AssigneeSilicon Storage Technology, Inc.
InventorsSohrab Kianian, Dana Lee
Estimating the term…
A full programmable and erasable non-volatile floating gate memory array uses an array of memory cells arranged in a plurality of rows and columns. Each cell is of the type with a first region, a spaced apart second region and a channel region in between. A floating gate is disposed over and is insulated from a portion of the channel region and the second region. An electrically conductive gate has a first section disposed over and insulated from the first region and is disposed and is adjacent to the floating gate and is insulated therefrom and has a second section disposed over the floating gate and is insulated therefrom. The cells are arranged in rows with the second region for connection to a common line. The control gate of each of the memory cells is for connecting to a word line associated with the row. Each column is connected to the first region of the memory cells arranged in the column. The array has a plurality of first transistors interposed in each row for connecting the second regions of the memory cells arranged in each row to the common line. Each of the plurality of first transistors has an associated first portion of the memory cells in each row. Each of the first transistor can be activated by an activating means to program the memory cells of the associated first portion.
In an array of non-volatile floating gate memory cells arranged in a plurality of rows and columns with each cell of the type having a first region, a spaced apart second region, with a channel region therebetween, a floating gate disposed over and insulated from a portion of said channel region and from a portion of said second region, an electrically conductive control gate having a first section disposed over and insulated from said first region and disposed adjacent to said floating gate and insulated therefrom and a second section disposed over said floating gate and insulated therefrom, said array comprising:
In an array of non-volatile floating gate memory cells arranged in a plurality of rows and columns with each cell of the type having a first region, a spaced apart second region, with a channel region therebetween, a floating gate disposed over and insulated from a portion of said channel region and from a portion of said second region, an electrically conductive control gate having a first section disposed over and insulated from said first region and disposed adjacent to said floating gate and insulated therefrom and a second section disposed over said floating gate and insulated therefrom, said array comprising:
Dependencies are inferred from the claim text.