US 5,852,576 AGranted

High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate

AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited

InventorsBinh Quang Le, Pau-Ling Chen, Shane Charles Hollmer, Shoichi Kawamura, Michael Shingche Chung, Vincent C. Leung, Masaru Yano

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Abstract

Two NMOS boost transistors have their sources connected to the high voltage input while their drains and gates are cross-connected. Two coupling capacitors connect two alternate phase clocks to the gates of the two cross-connected boost transistors. An NMOS pass transistor has its gate connected to the drain of one of the NMOS boost transistors, its source connected to the high voltage input, and its drain connected to the output. In an embodiment, two diode-connected regulation transistors connect the gates of the boost transistors to the high voltage input. These connections insure that the gates of the boost transistors and the gate of the pass transistor never reach voltages higher than one threshold voltage above the high voltage input. In another embodiment, two discharge transistors have their drains connected to a decode input, their sources connected to the gates of the boost transistors, and their gates connected to the positive power supply. By setting the decode input at zero volts, the voltages at the gates of the boost transistors and of the pass transistor are held at zero volts, thus disabling them. In the preferred embodiment, both the regulation transistors and the discharge transistors are included in the high voltage pass gate.

Claims25

Dependent claims

A flash erasable non-volatile memory having a high voltage switch, comprising:

a plurality of floating gate memory cells each having a control gate;
a word line coupled to the control gates of the plurality of floating gate memory cells;
a first NMOS boost transistor having a source, a drain, and a gate;
a second NMOS boost transistor having a source, a drain, and a gate;
a first NMOS coupling capacitor having first and second terminals;
a second NMOS coupling capacitor having first and second terminals;
an NMOS pass transistor having a source, a drain, and a gate;
a first NMOS discharge transistor having a source, a drain, and a gate;
and
a second NMOS discharge transistor having a source, a drain, and a gate;
wherein the first NMOS boost transistor drain is connected to the second NMOS boost transistor gate and the second coupling capacitor second terminal;
wherein the second NMOS boost transistor drain is connected to the first NMOS boost transistor gate, the first coupling capacitor second terminal, and the pass transistor gate;
wherein the high voltage switch input is coupled to the NMOS pass transistor source, the first NMOS boost transistor source, and the second NMOS boost transistor source;
wherein the first NMOS coupling capacitor first terminal is connected to a first clock input, and the second NMOS coupling capacitor first terminal is connected to a second clock input;
wherein the NMOS pass transistor drain is connected to the word line;
wherein the first NMOS discharge transistor source is connected to the first NMOS boost transistor drain;
wherein the second NMOS discharge transistor source is connected to the second NMOS boost transistor drain.

14 more elements

A flash erasable non-volatile memory having a high voltage switch, comprising:

a plurality of floating gate memory cells each having a control gate;
a word line coupled to the control gates of the plurality of floating gate memory cells;
a first NMOS boost transistor having a source, a drain, and a gate;
a second NMOS boost transistor having a source, a drain, and a gate;
a first NMOS coupling capacitor having first and second terminals;
a second NMOS coupling capacitor having first and second terminals;
an NMOS pass transistor having a source, a drain, and a gate;
a first NMOS regulation transistor having a source, a drain, and a gate;
and
a second NMOS regulation transistor having a source, a drain, and a gate;
wherein the first NMOS boost transistor drain is connected to the second NMOS boost transistor gate and the second coupling capacitor second terminal;
wherein the second NMOS boost transistor drain is connected to the first NMOS boost transistor gate, the first coupling capacitor second terminal, and the pass transistor gate;
wherein the high voltage switch input is coupled to the NMOS pass transistor source, the first NMOS boost transistor source, and the second NMOS boost transistor source;
wherein the first NMOS coupling capacitor first terminal is connected to a first clock input, and the second NMOS coupling capacitor first terminal is connected to a second clock input;
wherein the NMOS pass transistor drain is connected to the word line;
wherein the first NMOS regulation transistor source and gate are connected to the first NMOS boost transistor drain;
wherein the second NMOS regulation transistor source and gate are connected to the second NMOS boost transistor drain;
and
wherein the high voltage switch input is connected to the first NMOS regulation transistor drain and the second NMOS regulation transistor drain.

16 more elements

A flash erasable non-volatile memory having a high voltage switch, comprising:

a plurality of floating gate memory cells each having a control gate;
a word line coupled to the control gates of the plurality of floating gate memory cells;
a first NMOS boost transistor having a source, a drain, and a gate;
a second NMOS boost transistor having a source, a drain, and a gate;
a first NMOS coupling capacitor having first and second terminals;
a second NMOS coupling capacitor having first and second terminals;
an NMOS pass transistor having a source, a drain, and a gate;
a first NMOS regulation transistor having a source, a drain, and a gate;
a second NMOS regulation transistor having a source, a drain, and a gate;
a first NMOS discharge transistor having a source, a drain, and a gate;
and
a second NMOS discharge transistor having a source, a drain, and a gate;
wherein the first NMOS boost transistor drain is connected to the second NMOS boost transistor gate and the second coupling capacitor second terminal;
wherein the second NMOS boost transistor drain is connected to the first NMOS boost transistor gate, the first coupling capacitor second terminal, and the pass transistor gate;
wherein the high voltage switch input is coupled to the NMOS pass transistor source, the first NMOS boost transistor source, and the second NMOS boost transistor source;
wherein the first NMOS coupling capacitor first terminal is connected to a first clock input, and the second NMOS coupling capacitor first terminal is connected to a second clock input;
wherein the NMOS pass transistor drain is connected to the word line;
wherein the first NMOS regulation transistor source and gate are connected to the first NMOS boost transistor drain;
wherein the second NMOS regulation transistor source and gate are connected to the second NMOS boost transistor drain;
wherein the high voltage switch input is connected to the first NMOS regulation transistor drain and the second NMOS regulation transistor drain;
wherein the first NMOS discharge transistor source is connected to the first NMOS boost transistor drain;
and
wherein the second NMOS discharge transistor source is connected to the second NMOS boost transistor drain.

20 more elements

Dependencies are inferred from the claim text.