US 5,852,575 A · Apparatus and method for reading multi-level data stored in a semiconductor memory

Abstract

A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.

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Drawings

Claims27

Dependent claims

A semiconductor memory device comprising:

a plurality of memory cells arranged in rows and columns, for storing multi-level data, each of said memory cells having a gate and a current path;
a plurality of word lines connected to the gates of said memory cells;
a plurality of bit lines, each of the bit lines being connected to one end of the current path of at least one of the memory cells;
first selecting means connected to said word lines, for selecting one of said word lines in accordance with an address signal;
voltage-applying means connected to said first selecting means, for generating different voltages sequentially and for applying the different voltages to said first selecting means during a data-reading operation to read out data from said memory cells;
second selecting means for selecting at least two of said bit lines one after another in accordance with an address signal, while one of said word lines is selected by said first selecting means and while a voltage is applied from said voltage-applying means to the selected word line, in order to read data from said memory cells;
and
a sense amplifier, the sense amplifier being selectively coupled to said bit line selected by said second selecting means, for sequentially detecting potentials of said bit line,
wherein said sense amplifier has one sense level, and detects the current flowing through said memory cell selected by said second selecting means using the sense level.

6 more elements

A semiconductor device comprising:

a plurality of memory cells arranged in rows and columns, each of said memory cells storing multi-level data representative of at least two bits of information, each of said memory cells having a gate and a current path;
a plurality of word lines connected to the gates of said memory cells;
a plurality of bit lines, each of the bit lines being connected to one end of the current path of at least one of the memory cells;
first selecting means connected to said word lines, for selecting one of said word lines in accordance with an address signal;
voltage-applying means connected to said first selecting means, said voltage-applying means having a plurality of reference cells, respective ones of said reference cells being set at different reference potentials, said voltage-applying means applying different reference potentials generated by said references cells to said first selecting means sequentially during a data-reading operation to read data out from the memory cells;
second selecting means for selecting at least two of said bit lines one after another in accordance with an address signal, while one of said word lines is selected by said first selecting means and while a reference potential is applied from said voltage-applying means to the selected word line, in order to read data from said memory cells;
and
a sense amplifier, the sense amplifier being selectively coupled to said bit line selected by said second selecting means, for sequentially detecting potentials of said bit line,
wherein said sense amplifier has one sense leve, and detects the current flowing through said memory cell selected by said second selecting means using the sense level.

6 more elements

A semiconductor memory device comprising:

a plurality of memory cells arranged in rows and columns, for storing multi-level data, each of said memory cells having a gate and a current path;
a plurality of word lines connected to the gates of said memory cells;
a plurality of bit lines, each of the bit lines being connected to one end of the current path of at least one of the memory cells;
first selecting means connected to said word lines, for selecting one of said word lines in accordance with an address signal;
voltage-applying means connected to said first selecting means, said voltage-applying means including:
a voltage-generating circuit for dividing a power-supply voltage into a plurality of different voltages which are to be applied to said word lines, and for applying the different voltages sequentially to said first selecting means;
and
a stop circuit connected to said voltage-generating circuit and having first, second, and third reference cells which are used to set at a potential the word line selected by said first selecting means and which have a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage, respectively, said stop circuit stopping said voltage-generating circuit when the voltage generated by said voltage-generating circuit reaches one of said first, second, and third threshold voltages;
second selecting means for selecting at least two of said bit lines one after another in accordance with an address signal, while one of said word lines is selected by said first selecting means and while a voltage is applied from said voltage-applying means to the selected word line, in order to read data from said memory cells;
and
a sense amplifier, the sense amplifier being selectively coupled to said bit line selected by said second selecting means, for sequentially detecting potentials of said bit line,
wherein said sense amplifier has one sense level, and detects the current flowing through said memory cell selected by said second selecting means using the sense level.

9 more elements

A semiconductor memory device comprising:

a plurality of memory cells arranged in rows and columns, for storing multi-level data, each of said memory cells having a gate and a current path;
a plurality of word lines connected to the gates of said memory cells;
a plurality of bit lines, each of the bit lines being connected to one end of the current path of at least one of the memory cells;
first selecting means connected to said word lines, for selecting one of said word lines in accordance with an address signal;
voltage-applying means connected to said first selecting means, said voltage-applying means including:
a voltage-generating circuit for dividing a power-supply voltage into a plurality of different voltages which are to be applied to said word lines, and for applying the different voltages sequentially to said first selecting means;
and
a stop circuit connected to said voltage-generating circuit and having first, second, third, and fourth reference cells which are used to set at a potential the word line selected by said first selecting means and which have a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, and a fourth threshold voltage higher than the third threshold voltage, respectively, said stop circuit stopping said voltage-generating circuit when the voltage generated by said voltage-generating circuit reaches one of an intermediate voltage between said first and second threshold voltages, an intermediate voltage between said second and third threshold voltages, and an intermediate voltage between said third and fourth threshold voltages;
second selecting means for selecting at least two of said bit lines one after another in accordance with an address signal, while one of said word lines is selected by said first selecting means and while a voltage is applied from said voltage-applying means to the selected word line, in order to read data from said memory cells;
and
a sense amplifier, the sense amplifier being selectively coupled to said bit line selected by said second selecting means, for sequentially detecting potentials of said bit line,
wherein said sense amplifier has one sense level, and detects the current flowing through said memory cell selected by said second selecting means using the sense level.

9 more elements

A method of reading multi-level data stored in at least two of a plurality of memory cells by selecting a word line and at least two bit lines, said method comprising the steps of:

applying a first potential to the selected word line to sequentially detect current flowing through at least two memory cells, which are connected to the word line, with a sense amplifier, and latching a first signal output from the sense amplifier in a first latch circuit;
applying a second potential higher than the first potential to the selected word line to sequentially detect current flowing through said at least two memory cells, and latching a second signal output from the sense amplifier in a second latch circuit;
applying a third potential higher than the second potential to the selected word line to sequentially detect current flowing through said at least two memory cells, and latching a third signal output from the sense amplifier in a third latch circuit;
and
generating digital data from the first, second, and third signals latched in said first, second, and third latch circuits,
wherein the sense amplifier detects the current flowing through said at least one memory cell using one sense level, and outputs the first, second, and third signals.

3 more elements

Dependencies are inferred from the claim text.

Description19,320 words

Summary1,818 words

#1. Field of the Invention

#The present invention relates to a semiconductor memory such as a ROM (Read Only Memory) storing multi-level data, and more particularly to an apparatus and method for reading multi-value data from a ROM.

#2. Description of the Related Art

Brief description of the drawings55 figures

#FIG. 1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the invention;

#FIG. 2 is a circuit diagram of the output circuits used in the memory device shown in FIG. 1;

#FIG. 3 is circuit diagram of the sense amplifier incorporated in the memory device shown in FIG. 1;

Detailed description16,628 words

#Embodiments of the present invention will be described below, with reference to the accompanying drawings.

#A semiconductor memory according to the first embodiment will be described, with reference to FIGS. 1 to 11.

#As shown in FIG. 1, the memory cell array 1 of the semiconductor memory has memory cells M1, M2, M3, M4, . . . which are MOS transistors and which are arranged in rows and columns. Word lines W1, W2, W3, . . . extend along the rows of memory cells, and bit lines B1, B2, B4, B5, B6, B7, B8, . . . extend along the columns of memory cells. Each memory cell has its gate connected to a word line and its drain connected to a bit line. The source of each memory cell is grounded. The word lines W1, W2, W3, . . . are connected to a row decoder 2.

Facts

Application

08/819,052Filed 18 Mar 1997 · continuation

Priority

JP 5-19387612 Jul 1993

Granted

22 Dec 1998

Term ended

8 Jul 2014

Estimated · how

20 years from earliest known nonprovisional domestic filing. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination. Patent term adjustment is unavailable; no adjustment was added.

Classification9 codes

G11C 11/5692
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: read-only digital stores…
G11C 11/56
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor: using storage elements…
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits

Apparatus and method for reading multi-level data stored in a semiconductor memory

Life of this patent

Apparatus and method for reading multi-level data stored in a semiconductor memory

Life of this patent

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims27

Description19,320 words

Drawings

Classification9 codes

Description19,320 words