Small-sized static random access memory cell

An SRAM cell, comprising:

• a dual-use line for receiving a word and a power supply voltage;
• a first load element connected between the dual-use line and a first storage node;
• a second load element connected between the dual-use line and a second storage node;
• a first NMOS driver transistor connected between the first storage node and ground;
• a second NMOS driver transistor connected between the second storage node and ground;
• a first PMOS access transistor connected between the first storage node and a bit line, the first PMOS access transistor having a gate connected to the dual-use line;
• a second PMOS access transistor connected between the second storage node and a complementary bit line, the second PMOS access transistor having a gate connected to the dual-use line;
• a first current distributing element connected between the bit line and the power supply voltage for distributing current to the bit line;
• and
• a second current distributing element connected between the complementary bit line and the power supply voltage for distributing current to the complementary bit line.

An SRAM cell comprising:

• a line used as both a word line and a power supply voltage line;
• a first load element having a first and a second terminal, the first terminal being connected to the line;
• a second load element having a first and a second terminal, the first terminal being connected to the line;
• a first diode connected between the second terminal of the first load element and a first storage node;
• a second diode connected between the second terminal of the second load element and a second storage node;
• a first NMOS driver transistor connected between the first storage node and ground;
• a second NMOS driver transistor connected between the second storage node and ground;
• a first PMOS access transistor connected between the first storage node and a bit line, the first PMOS access transistor having a gate connected to the line;
• a second PMOS access transistor connected between the second storage node and a complementary bit line, the second PMOS access transistor having a gate connected to the line.