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US 5,852,571 AGranted
Nonvolatile ferroelectric memory with folded bit line architecture
AssigneeMicron Technology, Inc.
InventorWayne I. Kinney
Life of this patent
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Abstract
A ferroelectric memory device has a folded bit line architecture. The ferroelectric memory device may include a selectable upper even memory cell connected to an upper even bit line, a sense amplifier having a first input and a second input; control circuitry operable to connect an upper odd bit line to a lower odd bit line at the first input of the sense amplifier, to connect the upper even bit line to the second input of the sense amplifier, and to isolate a lower even bit line from the second input of the sense amplifier; and a selectable lower odd reference cell, connected to the lower odd bit line.
Claims21
A ferroelectric memory device having a folded bit line architecture, comprising:
- a selectable upper even memory cell, coupled to an upper even bit line;
- a first sense amplifier having a first input and a second input;
- control circuitry operable to couple an upper odd bit line to a lower odd bit line at the first input of the first sense amplifier, to couple the upper even bit line to the second input of the first sense amplifier, and to isolate a lower even bit line form the second input of the first sense amplifier, wherein the sum of the length of the upper odd bit line and the length of the lower odd bit line equals substantially twice the length of the upper even bit line;
- and
- a selectable lower odd reference cell coupled to the lower odd bit line.
2 more elements
A method of operating a ferroelectric memory, comprising the steps of:
- (a) isolating a lower even bit line from an upper even bit line;
- (b) activating a memory cell coupled to the upper even bit line to place a voltage onto the upper even bit line;
- (c) activating a reference cell connected to an odd bit line to place a voltage onto the odd bit line, wherein the length of the odd bit line equals substantially twice the length of the upper even bit line;
- and
- (d) differentially comparing said voltage on the odd bit line to said voltage on the upper even bit line.
2 more elements
A ferroelectric memory device having a folded bit line architecture, comprising:
- a first even memory cell having a first even ferroelectric capacitor, the first even ferroelectric capacitor having a first plate and a second plate, the first plate being coupled to a first plate line and the second plate being coupled to an even bit line through a first access transistor, the first access transistor being controlled by a first even word line;
- a second even memory cell having a second even ferroelectric capacitor, the second even ferroelectric capacitor having a third plate and a fourth plate, the third plate being coupled to a second plate line and the fourth plate being coupled to the even bit line through a second access transistor, the second access transistor being controlled by a second even word line;
- a first odd memory cell having a first odd ferroelectric capacitor, the first odd ferroelectric capacitor having a fifth plate and a sixth plate, the fifth plate being coupled to the second plate line and the sixth plate being coupled to an odd bit line through a third access transistor, the third access transistor being controlled by a first odd word line;
- and
- a second odd memory cell having a second odd ferroelectric capacitor, the second odd ferroelectric capacitor having a seventh plate and an eighth plate, the seventh plate being coupled to a third plate line and the eighth plate being coupled to the odd bit line through a fourth access transistor, the fourth access transistor being controlled by a second odd word line, wherein the length of the odd bit line is substantially doubled when the reference cell is coupled to the odd bit line, and wherein the length of the even one bit line is substantially doubled when the reference cell is coupled to the even bit line.
2 more elements
A ferroelectric memory array comprising:
- a plurality of selectable upper memory cells, each of said plurality of selectable upper memory cells coupled to one of a plurality of first upper bit lines;
- a plurality of selectable lower reference cells, each of said plurality of selectable lower reference cells coupled to one of a plurality of second lower bit lines;
- and
- a plurality of control circuits, each of said plurality of control circuits operable to couple one of a plurality of second upper bit lines to one of said plurality of second lower bit lines at a first input of a sense amplifier, to couple one of said plurality of first upper bit lines to a second input of the sense amplifier, and to isolate one of said plurality of first lower bit lines from the second input of the sense amplifier, wherein the sum of the length of each respective second upper bit line and the length of each respective second lower bit line equals substantially twice the length of each respective first upper bit line.
1 more element
Dependencies are inferred from the claim text.