Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones

An LSI layout design method of designing, according to circuit design information, a layout of cells and cell interconnection on a semiconductor substrate and preparing a mask pattern based on the layout thus designed, comprising:

• an input processing for entering circuit design information and the information of a cell group which can be placed;
• a cell placing processing for selecting cells from said cell group which can be placed, and for two-dimensionally placing said cells thus selected on a plane according to said circuit design information, thereby to design a layout of said selected cells arranged in a plurality of parallel cell rows;
• a wiring zone height estimating processing for estimating, in said cell layout designed by said cell placing processing, the wiring zone height or length in a direction at a right angle to said cell rows, of a necessary wiring zone required between two adjacent cell rows for the purpose of wiring;
• a cell changing processing for amending said cell layout by changing a cell placed on said cell layout designed by said cell placing processing, to a cell which has the same specifications and a different shape or a different cell terminal position and which is contained in said cell group which can be placed, thereby to reduce the area of a pure wiring zone disposed solely for the purpose of wiring, said pure wiring zone being required for assuring said wiring zone height of said necessary wiring zone, in addition to the over-the-cell wiring zones where wiring can be made on cells;
• a wiring processing for designing a layout of cell interconnection according to said cell layout amended by said cell changing processing and according to said circuit design information;
• and
• a mask pattern preparing processing for preparing a mask pattern based on said layout of cell and cell interconnection designed by said processings above-mentioned,
• wherein said cell changing processing comprises:
• a cell row height determining processing for obtaining a cell row height such that said wiring zone height of said necessary wiring zone is assured in said over-the-cell wiring zone;
• a cell merge processing for (i) acquiring, from said information entered by said input processing relating to said cell group which can be placed, the figure information of placement and wiring of transistors of cells forming each cell row, (ii) merging a plurality of cells of one cell row or two adjacent cell rows, into one cell, and (iii) vertically or horizontally compacting the figure of placement and wiring of the transistors of said plurality of cells such that the height of each of said cell rows is equal to said cell row height obtained by said cell row height determining processing;
• and
• a processing for changing a plurality of cells out of said cells placed by said cell placing processing, to a cell obtained by said cell merge processing.