Automatic clock signal phase adjustment in which a pattern including 0's is detected and integrated to effect the phase adjustment

An automatic clock signal phase adjusting circuit for use with a digital magnetic recording and reproducing apparatus adopting a partial response class IV coding method, said automatic clock signal phase adjusting circuit comprising:

• pattern detecting means for simultaneously detecting patterns "1, 0, -1" and "-1, 0, 1" from a reproduced signal;
• level detecting means for detecting respective levels of said reproduced signal corresponding to the patterns "1, 0, 1" and "-1, 0, 1" in effect when said pattern detecting means detects 0's from the two patterns to produce respective first and second level signals;
• integrating means for integrating said respective first and second level signals;
• clock reproducing means for reproducing a clock signal from said reproduced signal;
• and
• phase adjusting means for adjusting the phase of said clock signal reproduced by said clock reproducing means by detecting equality of said respective integrated first and second level signals and adjusting the phase of said clock signal based on the detected equality of said respective integrated first and second level signals.