US 5,852,416 AGranted

High speed arithmetic logic circuit

AssigneesCanon Kabushiki Kaisha, Tadahiro Ohmi

InventorsTadahiro Ohmi, Katsuhisa Ogawa

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Abstract

In order to realize a highly integrated, highly parallel system, there is provided a semiconductor circuit in which two or more input terminals are commonly connected to the non-inverting input terminal (+) of an operational amplifier via first capacitance means, the inverting input terminal (-) of the operational amplifier is connected to the output terminal of the operational amplifier via a second capacitance means two or more input terminals are commonly connected to the inverting input terminal via third capacitance means, and a first floating node as the node between the non-inverting input terminal (+) and the first capacitance means and a second floating node as the node between the inverting input terminal (-) and the second and third capacitance means are connected to reset means.

Claims31

Dependent claims

A semiconductor device comprising:

an operational amplifier circuit;
first capacitance means having one terminal connected to at least two input terminals and the other terminals connected to a non-inverting input terminal of said operational amplifier circuit, wherein the respective terminals of said first capacitance means are connected commonly, thereby constituting a first floating node;
second capacitance means having one terminal connected to an inverting input terminal of said operational amplifier circuit and the other terminals connected to an output of said operational amplifier circuit;
third capacitance means having one terminal connected respectively to at least two input terminals and the other terminals connected to the inverting input terminal of said operational amplifier circuit, wherein the other terminals of said third capacitance means and the one terminal of said second capacitance means are respectively connected commonly to constitute a second floating gate node;
and
reset means for resetting said first and second floating nodes.

3 more elements

A semiconductor device comprising:

an operational amplifier circuit;
first capacitance means having one terminal connected respectively to at least two input terminals, and the other terminals connected respectively to a non-inverting input terminal of said operational amplifier circuit, wherein the other terminals of said first capacitance means are connected commonly to constitute a first floating gate;
second capacitance means having one terminal connected to an inverting input terminal of said operational amplifier circuit, and the other terminals connected to an output of said operational amplifier circuit, wherein the one terminal of said second capacitance means are connected commonly to constitute a second floating node;
and
reset means for resetting the first and second floating nodes.

2 more elements

Dependencies are inferred from the claim text.