Charge redistribution analog-to-digital converter with system calibration

A charge redistribution analog-to-digital converter, comprising:

• a sampling capacitor responsive to a sampling input of the analog-to-digital converter,
• a capacitor array operatively connected to the sampling capacitor,
• an offset correcting circuit operatively connected in parallel with the capacitor array and responsive to the sampling input of the analog-to-digital converter,
• a gain correcting circuit operatively connected in parallel with the sampling capacitor and responsive to the sampling input of the analog-to-digital converter, and
• wherein each of the offset correcting circuit and the gain correcting circuit comprises a series of memory elements and a capacitor array, each array comprising a series of capacitors operatively connected to respective switches, wherein the switches of the gain correcting circuit are respectively responsive to the memory elements of the gain correcting circuit, and wherein the switches of the offset correcting circuit are respectively responsive to the memory elements of the offset correcting circuit.

A charge redistribution analog-to-digital converter, comprising:

• capacitive sampling means responsive to a sampling input means of the analog-to-digital converter for sampling a voltage at the sampling input means,
• capacitive digital-to-analog conversion array means operatively connected to the capacitive sampling means and for testing a stored quantity of charge,
• means for correcting an offset of the analog-to-digital converter, operatively connected in parallel with the capacitive digital-to-analog conversion array means capacitor array, and responsive to the sampling input means of the analog-to-digital converter,
• means for correcting a gain of the analog-to-digital converter, operatively connected in parallel with the capacitive sampling means and responsive to the sampling input means of the analog-to-digital converter,
• wherein the means for correcting an offset and the means for correcting a gain each comprise means for storing a calibration value,
• wherein the means for correcting an offset and the means for correcting a gain each comprise capacitive array means, which comprises a series of capacitive means operatively connected to respective means for switching,
• wherein the means for switching of the means for correcting a gain are responsive to respective elements of the means for storing of the means for correcting a gain, and
• wherein the means for switching of the means for correcting an offset are responsive to respective elements of the means for storing of the means for correcting an offset.

An analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, comprising:

• receiving a digital gain calibration signal,
• adjusting a gain of the analog-to-digital converter by an amount determined by the digital gain calibration signal received in the step of receiving a digital gain calibration signal,
• receiving a digital offset calibration signal,
• adjusting an input offset of an input of the analog-to-digital converter by an amount determined by the digital offset calibration signal received in the step of receiving a digital offset calibration signal, and
• after the steps of adjusting, converting an analog voltage to a digital value by successively testing a sampled charge with a capacitive network using the analog-to-digital converter, wherein the steps of adjusting are performed by adjusting capacitances used in the step of converting.

An analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, comprising:

• receiving a first voltage defining a first user-selected voltage range,
• adjusting an input offset of an input of the analog-to-digital converter,
• adjusting a gain of the analog-to-digital converter,
• after the steps of adjusting, converting an analog voltage to a digital value by successively testing a sampled charge with a capacitive network using the analog-to-digital converter, wherein the steps of adjusting and the step of converting are performed with reference to the first user-selected voltage range,
• receiving a second voltage defining a second user-selected voltage range,
• again adjusting an input offset of an input of the analog-to-digital converter,
• again adjusting a gain of the analog-to-digital converter, and
• after the steps of again adjusting, again converting an analog voltage to a digital value by successively testing a sampled charge with a capacitive network using the analog-to-digital converter, wherein the steps of again adjusting and the steps of again converting are performed with reference to the second user-selected voltage range.