Multi-protocol data bus system
AssigneeThomson Consumer Electronics, Inc.
InventorsGabriel Alfred Edde, Michael David Landis
Life of this patent
Estimating the term…
Abstract
A multi-protocol serial data bus system includes two clock lines and a data line. A controller generates a first clock signal and a first data signal according to a first serial data bus protocol during a first mode of operation of the system, and generates a second clock signal and a second data signal according to a second serial data bus protocol during a second mode of operation. The first clock signal and the first data signal are provided on the first and third signal paths, respectively, during the first mode of operation. The second clock signal and the second data signal are provided on the second and third signal paths, respectively, during the second mode of operation.
Claims20
A system comprising:
- a data bus comprising first, second and third signal paths;
- and
- control means for generating a first clock signal and a first data signal according to a first data bus protocol during a first mode of operation of said system, and for generating a second clock signal and a second data signal according to a second data bus protocol during a second mode of operation;
- said control means providing said first clock signal and said first data signal on said first and third signal paths, respectively, in accordance with said first data bus protocol during said first mode of operation, and providing said second clock signal and said second data signal on said second and third signal paths, respectively, in accordance with said second data bus protocol during said second mode of operation.
A system comprising:
- a data bus comprising first, second and third signal paths;
- a first device coupled to said first and third signal paths;
- a second device coupled to said second and third signal paths;
- control means for generating a first clock signal and a first data signal according to a first data bus protocol during a first mode of operation of said system, for generating a second clock signal and a second data signal according to a second data bus protocol during a second mode of operation, and for generating a control signal indicating whether said system is in said first or said second mode of operation;
- and
- switch means responsive to said control signal for coupling said first data signal to said third signal path during said first mode of operation and for coupling said second data signal to said third signal path during said second mode of operation;
- said control means providing said first clock signal on said first signal path in accordance with said first data bus protocol for controlling said first device during said first mode of operation, and providing said second clock signal on said second signal path in accordance with said second data bus protocol for controlling said second device during said second mode of operation.
A system comprising:
- a serial data bus comprising first, second and third signal paths;
- first means coupled only to said first and third signal paths for processing data in response to a first pair of signals exhibiting a first predetermined timing relationship in accordance with a first data bus protocol;
- said first pair of signals being received via said first and third signal paths;
- second means coupled only to said second and third signal paths for processing data in response to a second pair of signals exhibiting a second predetermined timing relationship in accordance with a second data bus protocol;
- said second pair of signals being received via said second and third signal paths;
- control means coupled to said data bus for generating a clock signal and a data signal during each of first and second modes of operation of said system, said clock signal and said data signal exhibiting said first predetermined timing relationship in accordance with said first data bus protocol during said first mode of operation and exhibiting said second predetermined timing relationship in accordance with said second data bus protocol during said second mode of operation;
- said control means providing said clock signal and said data signal to said first and third signal paths, respectively, for providing said first pair of signals for controlling only said first means during said first mode of operation, and providing said clock signal and said data signal to said second and third signal paths, respectively, for providing said second pair of signals for controlling only said second means during said second mode of operation;
- and
- bias means for establishing a predetermined signal level on one of said first and second signal paths during one of said first and second modes of operation.
Dependencies are inferred from the claim text.