Three-state CMOS output buffer circuit

A three-state CMOS output buffer circuit comprising:

• a final amplifier stage comprising a pull-up transistor and a pull-down transistor connected between a voltage supply and ground and having a common output node;
• and
• control circuitry for driving the final amplifier stage comprising:
• a first logic gate supplied with an input data signal and an enable/disable signal for activating a three-state mode in which the pull-up transistor and the pull-down transistor are both deactivated, the first logic gate driving the pull-up transistor;
• and
• a second logic gate supplied with said input data signal and enable/disable signal, the second logic gate driving the pull-down transistor;
• wherein said pull-up transistor has a bulk electrode connected to a switchable bulk line;
• and
• wherein an auxiliary circuit is provided which, as long as a voltage of the output node is not higher than a supply voltage of said voltage supply, keeps said switchable bulk line connected to the voltage supply;
• wherein said auxiliary circuit comprises switching means which as long as the voltage of the output node is not higher than the supply voltage are activated to connect said switchable bulk line to the supply voltage, and driving means which when the voltage of the output node exceeds the supply voltage deactivate said switching means;
• said first logic gate comprising means for transferring the voltage of the output node to said switchable bulk line when the voltage of the output node exceeds the supply voltage.

A three-state CMOS output buffer comprising:

• an output stage comprising a pull-up transistor and a pull-down transistor coupled between a voltage supply and ground and having a common output node, said pull-up transistor having a bulk electrode coupled to a first node;
• a first logic gate having a first input for receiving an enable/disable signal for activating a three-state mode in which the pull-up transistor and pull-down transistor are both deactivated, a second input for receiving a data signal and an output connected to a control electrode of said pull-up transistor;
• and
• an auxiliary circuit for connecting said first node to said voltage supply when a first condition is satisfied, and for connecting said first node to said output node when a second condition is satisfied;
• said first logic gate including transfer circuitry for transferring an output voltage of the output node to said first node when said second condition is satisfied.

A three-state CMOS output buffer comprising:

• an output stage comprising a pull-up transistor and a pull-down transistor coupled between a voltage supply and ground and having a common output node, said pull-up transistor having a bulk electrode coupled to a first node;
• a first logic gate having a first input for receiving an enable/disable signal for activating a three-state mode in which the pull-up transistor and pull-down transistor are both deactivated, a second input for receiving a data signal and an output connected to a control electrode of said pull-up transistor;
• and
• an auxiliary circuit for connecting said first node to said voltage supply when a first condition is satisfied, and for connecting said first node to said output node when a second condition is satisfied;
• said first logic gate including transfer circuitry for transferring an output voltage of the output node to said first node when said second condition is satisfied;
• wherein said first condition is satisfied when said output voltage is less than a supply voltage of said voltage supply;
• wherein said second condition is satisfied when said output voltage is greater than said supply voltage;
• wherein said auxiliary circuit comprises a first transistor connected between the power supply and the first node and having a bulk electrode connected to the first node and a second transistor connected between the output node and a control electrode of the first transistor, and having a control electrode connected to the voltage supply and a bulk electrode connected to the first node.