Phase adjusting circuit, system including the same and phase adjusting method
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Yamauchi
Life of this patent
Estimating the term…
Abstract
A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.
Claims18
A system comprising a first circuit for providing a reference clock signal and delay control information and a second circuit for operating in synchronization with the reference clock signal, the second circuit including:
- a circuit for providing an internal clock signal in a phase relationship with the reference clock signal;
- a delay circuit for delaying the internal clock signal for a predetermined delay time;
- an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time;
- and
- a delay control circuit for programmably changing the predetermined delay time in accordance with the delay control information,
- wherein the predetermined delay time is determined based on at least one of a first delay time generated by a line coupling the first circuit, the first circuit providing said reference clock signal to the second circuit, a second delay time generated by a line coupling the second circuit to the first circuit and a third delay time generated by a line which transfers the internal clock signal within the second circuit.
A phase adjusting method comprising the steps of:
- (a) determining a delay amount for an internal clock signal employed inside a second circuit for operating in synchronization with a reference clock signal generated by a first circuit, after the first circuit and the second circuit are implemented;
- and
- (b) adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal based on the delay amount,
- wherein the delay amount is determined based on at least one of a first delay time generated by a line coupling the first circuit, the first circuit providing said reference clock signal to the second circuit and a second delay time generated by a line coupling the second circuit to the first circuit.
A phase adjusting method comprising the steps of:
- (a) determining each delay amount for each of internal clock signals employed inside each of a plurality of second circuits for operating in synchronization with a reference clock signal generated by a first circuit, after the first circuit and the plurality of the second circuits are implemented;
- and
- (b) adjusting each phase difference between a phase of the reference clock signal and each phase of the internal clock signals based on the each delay amount,
- wherein the each delay amount is determined based on at least one of a first delay time generated by each line coupling the first circuit, the first circuit providing said reference clock signal to each of the plurality of the second circuits and a second delay time generated by each line coupling each of the plurality of the second circuits to the first circuit.
Dependencies are inferred from the claim text.