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US 5,852,375 AGranted
5v tolerant I/O circuit
AssigneeSilicon Systems Research Limited
InventorsTimothy Gerard Byrne, Brian T. Morley
Life of this patent
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Abstract
An integrated circuit has an I/O circuit that is connected to an I/O PAD. The I/O PAD may have greater voltage than the VDD associated with the integrated circuit so there is provided a switching circuit that is connected between the VDD and the I/O PAD. An output circuit is also provided that comprises n-channel transistors connected between the PAD and the ground. There is a cascode arrangement of p-channel transistors connected between the I/O PAD and VDD.
Claims6
An I/O circuit comprising:
- an I/O PAD connected to receive a first voltage;
- a first circuit having at least one first type transistor connected between a second voltage and the I/O PAD and a second circuit having at least one second type transistor connected between the I/O PAD and a third voltage;
- and
- a cascode arrangement of at least first and second transistors of the first type of transistors between the I/O PAD and the third voltage and a junction between a source of the first transistor and a drain of the second transistor being connected to a gate of the at least one second type of transistor.
1 more element
Dependencies are inferred from the claim text.