Multiplexing rate generator/counter circuit for controlling stepper motors

A multiplexing rate generator/counter circuit for controlling stepper motors comprising:

• an accumulator memory block,
• an edge detector,
• an axis scanning state machine,
• a position counter memory block,
• a position readback memory block,
• a configuration memory block,
• and an addend memory block;
• wherein
• at least one of said position counter memory block, said position readback memory block, said configuration memory block, or said addend memory block is an addressable memory block, a depth of said addressable memory block is equal to a number of motors being controlled by said circuit;
• and wherein
• said rate generator/counter circuit comprises a plurality of memory structures, each memory address in said memory structures represents a stepper motor in a subject system,
• said axis scanning state machine drives memory structure address lines in a circuitous manner to cycle among all stepper motors in said system such that at each memory address visit, a current state of said system is established in said rate generator/counter circuit based on information stored in each said memory address from a preceding cycle of said scanning state machine,
• an addition operation of said addend memory block and said accumulator memory block change accumulator memory block value in said accumulator memory block such that when said accumulator memory block overflows, step pulses are generated which are routed, along with axis direction signals from said configuration memory, to a subject stepper motor by means of a switch, said drive signals are then latched in non-multiplexing latches;
• such that
• an axis-scanning cycle frequency of N Hz supports a step rate of N Hz.