N-sided polygonal cell layout for multiple cell transistor
OwnerMing-Dou Ker, Tain-Shun Wu +1inventors
InventorsMing-Dou Ker, Tain-Shun Wu, Kuo-Feng Wang
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Abstract
A MOS transistor cell is disclosed for a multiple cell MOS transistor, such as in an ESD protection circuit, output buffer, etc. The transistor cell has a regular n-sided polygonal geometry, wherein n.gtoreq.8. A drain region is provided in a substrate which occupies an area with n-sided polygonal shaped boundaries. Surrounding the drain, is a channel region which occupies an n-sided polygonal shaped area. Surrounding the channel region is a source region provided in the substrate which occupies an annular shaped area having n-sided polygonal boundaries.
Claims33
A MOS cell, comprising:
- (a) a drain region formed in a substrate and occupying a regular n-sided polygonal shape, where n.gtoreq.8;
- (b) a channel region surrounding said drain region and occupying an annular shape with n-sided polygonal shaped boundaries;
- (c) a source region formed in said substrate, surrounding said channel region and occupying an annular shape with n-sided polygonal shaped boundaries;
- and
- (d) a well of the same conductivity type as said drain region formed in said substrate below said drain region and having n-sided polygonal shaped boundaries.
A multiple cell transistor, comprising:
- a plurality of identical cells having commonly connected identical regions, each of said cells comprising:
- (a) a drain region formed in a substrate and occupying a regular n-sided polygonal shape, where n.gtoreq.8;
- (b) a channel region surrounding said drain region and occupying an annular area having regular n-sided polygonal shaped boundaries;
- (c) a source region formed in said substrate, surrounding said channel region and occupying an annular area having regular n-sided polygonal shaped boundaries;
- and
- (d) a well of the same conductivity type as said drain region formed in said substrate below said drain region and having n-sided polygonal shaped boundaries.
An IC chip, comprising a multiple cell transistor formed from a plurality of identical cells having commonly connected identical regions, each of said cells comprising:
- (a) a drain region formed in a substrate and occupying a regular n-sided polygonal shape, where n.gtoreq.8;
- (b) a channel region surrounding said drain region and occupying an annular area having regular n-sided polygonal shaped boundaries;
- (c) a source region formed in said substrate, surrounding said channel region and occupying an annular area having regular n-sided polygonal shaped boundaries;
- and
- (d) a well of the same conductivity type as said drain region formed in said substrate below said drain region and having n-sided polygonal shaped boundaries.
Dependencies are inferred from the claim text.