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US 5,851,925 AGranted
Staining technique for semiconductor device for sem exposure
AssigneeNone recorded
InventorsMichelle Beh, Donald Grant
Life of this patent
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AssigneeNone recorded
InventorsMichelle Beh, Donald Grant
Estimating the term…
A method for staining a wafer containing a semiconductor device is disclosed which properly delineates the various layers of the semiconductor device and provides good contrast for proper testing and diagnosis of problems using a scanning electron microscope. After grinding, lapping and polishing a surface of the semiconductor device, the surface is ion beam etched, reactive ion etched and stained. The staining solution is made from 1 part by volume hydrofluoric acid, 3 parts by volume nitric acid, and 6 parts by volume acetic acid. The staining solution is cooled and subjected to a light to slow the reaction of the staining solution with the semiconductor device. This prevents structure collapse and under or over etching, and provides an easily controllable staining process.
A method for staining a wafer containing a semiconductor device comprising the steps of:
A method for diagnosis of defects in a wafer containing a semiconductor device comprising the steps of:
Dependencies are inferred from the claim text.
No related US applications are recorded in the indexed filing history.
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Preparing specimens for investigation including physical details of chemical methods covered elsewhere, e.g. G01N33/50, C12Q: polishing; Etching
Using non-ionising electromagnetic radiation, e.g. optical radiation: of integrated circuits
Preparing specimens for investigation including physical details of chemical methods covered elsewhere, e.g. G01N33/50, C12Q: staining;…
Investigating or analysing materials by determining their chemical or physical properties
Term ended 2 Jul 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention relates to a process for staining wafers containing semiconductor devices to provide contrast of the various layers of the semiconductor devices when viewed by an SEM (Scanning Electron Microscope).
Semiconductor devices are formed by depositing and patterning several layers of material. FIG. 1 schematically illustrates a conventional MOSFET device 10, and in particular an NMOS device. The NMOS device 10 comprises an N-type silicon substrate 11 and a P-well 12 which is formed in the substrate 11. N.sup.+ source and drain regions 14, 16, are formed at the surface of the P-well 12. The source and drain regions 14, 16, are separated by a channel 18. A gate structure is formed over the channel 18 between the source and drain regions 14, 16. More specifically, the gate 20 is formed from a conducting material such as polysilicon or polycide.
The gate 20 is separated from the surface of the P-well by a gate oxide SiO.sub.2 22. The gate 20 is covered by a dielectric 21 which may be oxide (SiO.sub.2) or nitride (Si.sub.3 N.sub.4). The dielectric 21 located on either side of the gate 20 forms oxide or nitride spacers 24, 26. Lightly doped regions 34 and 36 are provided to reduce the device hot carrier effects. Field oxide regions 38 are provided to separate adjacent MOS devices in an integrated circuit.
FIG. 1 illustrates a conventional MOS device;
FIG. 2 illustrates a flow chart of a conventional method for staining wafers containing semiconductor devices; and
FIG. 3 illustrates a flow chart of a method for staining wafers containing semiconductor devices according to the present invention.
The present invention is directed to a method for staining a wafer containing a semiconductor device which prevents structure collapse and over or under etching, eliminates metal coating, and provides better contrast for viewing under an SEM.
FIG. 3 shows a flow chart of a method 300 for staining wafers containing semiconductor devices according to the present invention. As shown in FIG. 3, the inventive method involves the following steps to stain the surface of the wafer:
1. As in the conventional method, grinding, lapping and polishing of the surface of the wafer are performed. A detailed description of these steps include: