Method for manufacturing a multi-layer wiring structure of a semiconductor device

Abstract

A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.

Dependencies are inferred from the claim text.