IGFET method of forming with silicide contact on ultra-thin gate

A method of forming an IGFET, comprising the steps of:

• forming a gate insulator on a semiconductor substrate;
• forming a gate material on the gate insulator;
• etching the gate material to form a gate with opposing sidewalls that extend to the gate insulator;
• implanting a dopant into the gate;
• depositing a contact material over the gate;
• and
• reacting the contact material with the gate to form a silicide contact on the gate and consume at least three-quarters of the gate without entirely consuming the gate, wherein a bottom surface of the gate and a lower region of the gate adjacent to the bottom surface of the gate are essentially undoped before reacting the contact material with the gate, and reacting the contact material with the gate pushes the dopant in the gate towards the substrate by way of a resultant interface between the silicide contact and the gate and consumes all of the gate except for the lower region of the gate and pushes a substantial concentration of the dopant into essentially all of the lower region of the gate to provide a substantial concentration of the dopant at the bottom surface of the gate.

A method of forming an IGFET, comprising the steps of:

• forming a gate insulator on a semiconductor substrate;
• forming a gate material on the gate insulator;
• etching the gate material to form a gate with opposing sidewalls that extend to the gate insulator;
• forming a source and a drain in the substrate, including implanting a dopant into the gate, the source and the drain;
• depositing a contact material over the gate, the source and the drain;
• and
• reacting the contact material with (i) the gate to form a silicide contact on the gate and consume at least one-half of the gate without entirely consuming the gate;
• (ii) the source to form a silicide contact on the source, and (iii) the drain to form a silicide contact on the drain.

A method of forming an IGFET that includes producing an ultra-thin polysilicon gate, comprising the following steps in the sequence set forth:

• forming a gate insulator over a semiconductor substrate;
• forming a polysilicon layer on the gate insulator;
• etching the polysilicon layer to form a polysilicon gate from an unetched portion of the polysilicon layer, wherein the polysilicon gate includes opposing sidewalls that extend to the gate insulator;
• implanting lightly doped source and drain regions into the substrate using the polysilicon gate as an implant mask;
• forming spacers in close proximity to the sidewalls of the polysilicon gate that partially cover the lightly doped source and drain regions;
• implanting heavily doped source and drain regions into the substrate using the polysilicon gate and the spacers as an implant mask;
• depositing a refractory metal over the polysilicon gate, the spacers and the heavily doped source and drain regions;
• and
• reacting the refractory metal with (i) the polysilicon gate to form a silicide contact on the polysilicon gate and consume at least one-half of the polysilicon gate without entirely consuming the polysilicon gate;
• (ii) the heavily doped source region to form a silicide contact on a source that includes the lightly and heavily doped source regions, and (iii) the heavily doped drain region to form a silicide contact on a drain that includes the lightly and heavily doped drain regions.