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US 5,851,882 AGranted
ZPROM manufacture and design and methods for forming thin structures using spacers as an etching mask
AssigneeMicron Technology, Inc.
InventorSteven T. Harshfield
Life of this patent
Estimating the term…
Abstract
A cost-competitive, dense, CMOS compatible ZPROM memory array design and method of manufacture is disclosed. The method of manufacture includes a novel method for forming extremely thin diodes and thin strips of other materials such as conductors by using oxide spacers as an etching mask.
Claims31
A method for manufacturing an array of memory cells, comprising:
- (a) forming a first doped region in a semiconducting substrate which is doped of opposite polarity to the substrate;
- (b) forming a second doped region within the first doped region which is doped of opposite polarity to the first doped region;
- (c) forming a first thin dielectric at the surface of the second doped region;
- (d) forming a first layer over the first thin dielectric and selectively etching the first layer to leave only strips of the first layer;
- (e) forming spacers on the edges of the remaining first layer strips to form a spacer pair;
- (f) anisotropically etching the remaining structure to remove the remaining portions of the first layer while simultaneously etching a portion of the exposed second doped region but leaving the spacers and structures underlying the spacers intact;
- (g) etching the remaining exposed portions of the first thin dielectric;
- (h) anisotropically etching the remaining structure to remove a portion of the second doped region between a given spacer pair, and to remove the remaining portion of the exposed second doped region outside of a given spacer pair such that the first doped region is exposed, but leaving the first spacers and structures underlying the spacers intact;
- (i) forming a thick dielectric over the resulting structure;
- (j) etching a portion of the thick dielectric and an underlying spacer to expose a portion of the second doped region which was previously underneath the spacer;
- (k) implanting the exposed portion of the second doped region with a dopant of opposite polarity to the second doped region to form a third doped region, thereby forming a diode at the junction of the second doped region and the third doped region;
- (l) forming a programmable element over the third doped region;
- and
- (m) forming a second layer and selectively etching the second layer to leave only strips of the second layer which run generally perpendicular to the remaining second doped region, whereby the second layer strips are electrically connected to the programmable element.
11 more elements
A method for manufacturing an array of memory cells, the method comprising the steps of:
- (a) forming a first doped region in a semiconductive substrate;
- (b) forming a second doped region in the first doped region, the second doped region being doped opposite the first doped region;
- (c) forming a first dielectric layer over the second doped region;
- (d) forming strips of material over the first dielectric layer;
- (e) forming spacers along the strips;
- (f) using the spacers as a mask, performing an etching operation to form a portion of the second doped region into a plurality of bit lines;
- (g) forming a second dielectric layer over the resulting structure;
- (h) forming contact holes over selected spacers and removing the selected spacers to expose selected portions of the second doped region;
- (i) doping the exposed selected portions of the second doped region to form a plurality of diodes;
- (j) operatively coupling programmable elements to the plurality of diodes;
- and
- (k) forming a plurality of word lines operatively coupled to at least one selected programmable element and extending generally perpendicular to the plurality of bit lines.
9 more elements
A method for manufacturing an array of memory cells, the method comprising the steps of:
- (a) forming a first doped region in a semiconductive substrate;
- (b) forming a second doped region in the first doped region, the second doped region being doped opposite the first doped region;
- (c) forming a first dielectric layer over the second doped region;
- (d) forming strips of material over the first dielectric layer;
- (e) forming spacers along the strips;
- (f) using the spacers as a mask, etching away the material strips, portions of the first dielectric layer, portions of the second doped region, and portions of the first doped region to form a plurality of bit lines;
- (g) forming a second dielectric layer over the resulting structure;
- (h) forming contact holes over selected spacers and removing the selected spacers to expose selected portions of the second doped region;
- (i) doping the exposed selected portions of the second doped region to form a plurality of diodes;
- (j) operatively coupling programmable elements to the plurality of diodes;
- and
- (k) forming a plurality of word lines operatively coupled to at least one selected programmable element and extending generally perpendicular to the plurality of bit lines.
9 more elements
Dependencies are inferred from the claim text.