Method of making monos flash memory for multi-level logic

A method of manufacture of a multi-level logic flash memory cell comprising the steps as follows:

• a) forming a tunnel oxide layer on a surface of a substrate having active regions;
• said substrate having a floating gate channel area and a MONOS channel area in said active regions;
• b) forming a poly floating gate electrode over said stacked gate channel region;
• c) forming an ONO layer over said poly floating gate electrode and the exposed surfaces of said tunnel oxide layer;
• d) forming a second polysilicon layer over said ONO layer;
• e) forming a pad oxide layer over said second polysilicon layer;
• f) forming a second nitride layer over said pad oxide layer;
• g) patterning said second nitride layer, said pad oxide layer, said second polysilicon layer, and said ONO layer forming a dual gate stack;
• the remaining portion of said second polysilicon layer forming a control gate electrode spanning across said poly floating gate electrode and said ONO layer over said MONOS channel region;
• h) forming shallow trench isolation regions in said substrate surrounding said dual gate stack;
• i) forming a source region in said substrate adjacent to said floating gate channel area and under a portion of said poly floating gate electrode;
• and forming a drain region in said substrate adjacent to said MONOS channel area and under a portion of said ONO layer;
• said source and drain regions orientated in a first direction;
• j) said control gate electrode and said floating gate electrode forming a poly floating gate transistor over said floating gate channel area;
• and said ONO layer and said control gate over said MONOS channel area forming a MONOS transistor over said MONOS channel area;
• a multi-level logic flash memory cell comprised of said poly floating gate transistor and said MONOS transistor.