US 5,851,878 A · Method of forming a rugged polysilicon fin structure in DRAM

Abstract

The capacitor for a DRAM is formed to have a textured bottom electrode using wet etch processes. A planarized dielectric layer is formed over the transfer FETs and bit line of a capacitor over bit line DRAM cell. A layer of silicon nitride is deposited over the planarized dielectric layer. A layer of silicon oxide is deposited over the silicon nitride layer and then a contact via is etched to expose the charge storage node of a transfer FET of the DRAM cell. A layer of polysilicon is deposited over the silicon oxide layer and into the contact via to connect the polysilicon layer to the charge storage node of the transfer FET. The polysilicon layer is patterned to define bottom capacitor plates. The silicon oxide layer is etched using hydrofluoric acid to expose the bottom surface of the polysilicon bottom capacitor plate. Next, a hydrofluoric acid dip is used to create a rugged polysilicon surface on the upper and lower surfaces of the bottom capacitor electrodes. A capacitor dielectric is provided and an upper capacitor electrode is formed to complete the DRAM cell.

Claims14

Dependent claims

A method of forming an integrated circuit memory device including charge storage capacitors, the method comprising:

providing a substrate having charge storage capacitor access circuitry formed thereon;
providing a first layer of dielectric material over the substrate and over and on the access circuitry;
providing a second dielectric layer over the first layer of dielectric material;
providing a barrier layer over the second dielectric layer;
providing a sacrificial layer over the barrier layer;
providing a first polysilicon layer over the sacrificial layer and patterning the layer of polysilicon to define a plurality of bottom capacitor electrodes separated by spaces;
providing a first wet etchant to the sacrificial layer through the spaces between the bottom capacitor electrodes, removing the sacrificial layer from between the barrier layer and the first polysilicon layer;
providing a capacitor dielectric layer over the bottom capacitor electrodes;
and
providing a second polysilicon layer over the capacitor dielectric layer to form an upper capacitor electrode.

7 more elements

Dependencies are inferred from the claim text.

Method of forming a rugged polysilicon fin structure in DRAM

Life of this patent

Method of forming a rugged polysilicon fin structure in DRAM

Life of this patent

Abstract

Claims14