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US 5,851,874 AGranted
Method of planarizing memory cells
AssigneeVanguard International Semiconductor Corporation
InventorsChan-Jen Kuo, Fu-Liang Yang
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Abstract
A planarzation process is crucial for submicron VLSI or ULSI fabrication, The method of the present invention comprises forming a stacked capacitor contact on a substrate, forming a first dielectric layer on the capacitor contact. Next an etching process is performed to etchback the first dielectric layer. Finally, a second dielectric layer is formed on the first dielectric layer. A thermal reflowing may be also used to increase the planarization.
Claims12
A method of planarizing a memory cell on semiconductor substrate, said method comprising the steps of:
- forming a capacitor contact on said semiconductor substrate;
- forming a first dielectric layer on said substrate and on said capacitor;
- etching said first dielectric layer to form side wall spacers on the side wall of said capacitor contact, and etching leaving at least a residue of said first dielectric layer atop of said capacitor contact;
- and
- forming a second dielectric layer on said first dielectric layer.
2 more elements
Dependencies are inferred from the claim text.