Process for manufacturing integrated capacitors in MOS technology

A method for manufacturing integrated capacitors for analog applications in MOS technology on a substrate of semiconductor material, consisting only of low temperature steps and starting from a substrate which already bears doping implantations for active components and on which an oxide is already formed, comprising the steps of:

• forming, on the oxide, a first conducting layer comprising polycrystalline silicon doped by low temperature ion implantation;
• patterning the first conducting layer to form a first plate of a capacitor and a MOS transistor gate electrode;
• forming a single capacitor dielectric layer by forming a oxide on and in contact with said first conducting material layer using only low temperatures less than about 700.degree. C. during the entire formation of said dielectric layer;
• and
• forming a second conducting material superimposed on and in contact with said capacitor dielectric layer to form a second plate of the capacitor;
• said low temperature not allowing for the displacement of said doping implantation.

A method of an integrated circuit including an analog capacitor and a MOS transistor, comprising:

• forming an oxide over a substrate containing doped regions for active device components;
• forming a polycrystalline silicon layer on the oxide;
• implanting ions into the polycrystalline silicon layer;
• forming a single capacitor dielectric layer on and in contact with the polycrystalline silicon layer by oxidation of tetraethylorthosilicate using only temperatures less than about 700.degree. C.;
• forming a conductive layer on and in contact with the capacitor dielectric layer;
• patterning the conductive layer and the capacitor dielectric to form an upper plate and a capacitor dielectric of the capacitor;
• patterning the polycrystalline silicon layer to form a lower plate of the capacitor and a gate electrode of the MOS transistor;
• and
• implanting impurities in exposed regions of the substrate not covered by the patterned polycrystalline silicon layer to form source and drain regions for the MOS transistor.