Method of fabricating BiCMOS devices
AssigneeHarris Corporation
InventorsAkira Ito, Michael David Church
Life of this patent
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Abstract
A BiCMOS process which provides both low voltage (digital) and high voltage (analog) CMOS devices. The high voltage NMOS devices have a compensated drain formed by the NPN and PNP base implants. The PNP base plus the high voltage NMOS drain carrier concentrations are both optimized by adjustment of the two variables N base implant dose and P base implant dose; this determines the NPN base carrier concentration which turns out to provide good NPN characteristics. Low voltage NMOS source and drain implants employ a higher dose and may also be used for the high voltage NMOS source. The NPN emitter doping may also be used for a contact to the high voltage NMOS drain contact.
Claims18
A method of fabrication of integrated circuits, comprising the steps of:
- (a) introducing N-type dopants into a semiconductor layer to simultaneously form the bases for PNP transistors and the drains of first NMOS transistors;
- and
- (b) introducing P-type dopants into said semiconductor layer to simultaneously form the bases for NPN transistors and compensate said drains of first NMOS transistors wherein said first NMOS transistors with drains having P-type and N-type dopants are characterized by a dopant concentration equal to the dopant concentration of the base dopants of said PNP transistors minus the dopant concentration of the base dopants of said NPN transistors.
A method of fabrication of integrated circuits, comprising the steps of:
- (a), introducing N-type dopants and P-type dopants into a silicon layer to form buried layers;
- (b) forming a silicon epilayer on said silicon layer;
- (c) forming insulating regions in said epilayer extending to said buried layers;
- (d) forming first polysilicon gates over said epilayer and between said insulating regions;
- (e) forming second polysilicon gates over said epilayer and between said insulating regions;
- (f) simultaneously forming N-type base regions in said epilayer and N-type drain regions in said epilayer adjacent a first plurality of said first gates;
- (g) forming N-type source and drain regions in said epilayer adjacent a second plurality of said second gates;
- (h) simultaneously forming P-type base regions in said epilayer and P-type compensation in said drain regions adjacent said plurality of said first gates wherein the dopant compensation in said drain regions is equal to the dopant concentration of the base dopants of N-type base dopants minus the dopant concentration of the P-type base dopants.
- (i) forming emitters in said N-type base regions;
- and
- (j) forming emitters in said P-type base regions.
Dependencies are inferred from the claim text.