Manufacture of application-specific IC

A method of manufacturing a semiconductor device, said method comprising the steps of:

• forming an insulating film over a metal wiring layer pattern formed on a substrate;
• forming a planarized film over the whole surface of said insulating film until the surface of said planarized film becomes flat, said planarized film being made of a material having a different property from said insulating film;
• removing said planarized film until the partial surface area of said insulating film formed on the top of said metal wiring pattern is exposed;
• forming a resist film on the surface of said exposed insulating film and said planarized film;
• patterning said resist film to form a resist pattern having an opening exposing at least one partial exposed surface area of said insulating film;
• and
• selectively removing a partial area of said insulating film not covered with said planarized film and said resist pattern and exposing a partial area of said metal wiring pattern,
• removing the exposed wiring pattern;
• wherein said metal wiring pattern is an overlying metal wiring pattern formed on the surface of a flat insulating film burying an underlying metal wiring pattern.

A method of manufacturing a semiconductor device, said method comprising the steps of:

• (a) providing a semiconductor substrate comprising:
• (a-1) a first level wiring layer;
• (a-2) second level wiring films;
• (a-3) a first interlevel insulating layer insulating the first level wiring layer and second level wiring films;
• and
• (a-4) a second interlevel insulating layer, which is formed over the second level wiring films so as to have convexes and concaves;
• (b) forming a first organic layer over the semiconductor substrate;
• (c) partially removing the first organic layer to expose the convexes of the second interlevel insulating layer;
• (d) selectively forming a second organic layer over the substrate except for a region where at least a part of the convexes of the second interlevel insulating layer remain exposed;
• and
• (e) selectively etching the exposed portion of the second interlevel insulating layer to form self-aligned windows over the second level wiring films, to expose a portion of a wiring pattern and
• (f) removing the exposed wiring pattern to achieve a desired configuration.

A method of manufacturing a multi-layered semiconductor device, said method comprising the steps of:

• (a) providing a substrate having a multi-layered structure that at least includes a first level wiring layer, a second level wiring layer and a first interlevel insulating layer insulating therebetween;
• (b) forming a second interlevel insulating layer over the multi-layered structure, the second interlevel insulating layer having convexes and concaves which transfer topography of the multi-layered structure;
• (c) forming a first mask layer having an aperture corresponding to the convex over the semiconductor substrate;
• (d) selectively forming a second mask layer over the substrate except for a region where at least a part of the convexes of the second interlevel insulating layer remain exposed;
• and
• (e) selectively etching the exposed portion of the second interlevel insulating layer through the first and second mask layers to form self-aligned windows over the second level wiring layer, to expose a portion of a wiring pattern and
• (f) removing the exposed wiring pattern to achieve a desired configuration.