Process for manufacturing a MOS-technology power device chip and package assembly

A method for making a MOS-technology power device chip and package assembly comprising the steps of:

• a) forming a plurality of elementary functional units in a semiconductor material layer, wherein each elementary unit includes
• a first doped region of a first conductivity type in said semiconductor layer, and
• a second doped region of a second conductivity type inside said first doped region;
• b) forming sub-pluralities of elementary functional units in said plurality of elementary functional units;
• c) contacting each second doped region of each sub-plurality by a same metal plate so that each metal plate corresponding to each sub-plurality is electrically insulated from one another;
• d) connecting each metal plate, through a bonding wire, to a source electrode pin of said package;
• e) separating said sub-pluralities of elementary functional units by regions of said semiconductor material layer where no elementary functional units are formed;
• f) covering said semiconductor material layer by a conductive insulated gate layer partially extending over each first doped region;
• g) contacting said insulated gate layer by gate metal mesh surrounding each metal plate;
• h) connecting said gate metal mesh to at least one gate metal pad;
• i) connecting said gate metal pad, by means of a bonding wire, to a pin of said package;
• and
• j) soldering a bottom surface of said chip onto a metal plate of said package.