Differential copper deposition on integrated circuit surfaces and method for same

A method of differentially depositing copper (Cu) on selected integrated circuit (IC) surfaces, the selected surfaces including conductive surfaces and a non-conductive surfaces applied to selected regions of the IC, the method comprising the steps of:

• a) exposing each selected surface to an ion gun source of inert ions;
• b) directly following step a), etching each selected surface to remove contaminants and undesired IC materials that have collected on the non-conductive surface while minimizing the energy of ions impinging into selected surfaces, whereby IC material is not removed from a surface by the kinetic energy of the ions introduced in Step a);
• and
• c) directly following step b), applying CVD Cu to each selected surface exposed in step a), forming a thick layer of Cu overlying conductive surfaces, and a thin layer of Cu overlying the non-conductive surfaces, whereby the exposure of the selected surfaces in step a) promotes variations in the rates at which Cu is deposited.

A method for selectively depositing Cu to form an interconnection stud between IC dielectric interlevels, the IC having a first IC surface including a conductive connection area with a conductive surface, a second IC surface having a non-conductive surface overlying the first surface, and a via, having vertical walls, between the non-conductive surface and the conductive surface, the method comprising the steps of:

• a) exposing the non-conductive surface and the conductive surface to an ion gun source of inert ions;
• b) directly following step a), etching the surfaces exposed in step a) to remove contaminants and undesired IC materials that have collected on the non-conductive surface while minimizing the energy of the ions impinging into the selected surfaces, whereby IC material is not removed from a surface by the kinetic energy of the ions introduced in Step a);
• c) directly following step b), applying CVD Cu to the surfaces exposed in step a), and the walls of the via, until less than a monolayer of Cu is accumulated on the non-conductive surface;
• and
• d) repeating steps a) through c) until the via is substantially filled with copper, whereby Cu interfaces between dielectric interlevels are formed without masking adjoining non-conductive surfaces.