Memory access controller utilizing cache memory to store configuration information

A memory access controller comprising:

• a memory address generator for generating an address for access to a memory;
• a memory configuration cache having a predetermined plurality of memory configuration cache entries, each memory configuration cache entry including an address range and a corresponding set of memory access parameters;
• a comparator connected to said memory address generator and said memory configuration cache comparing said address to said address range of each of said memory configuration cache entries;
• a memory interface connected to said memory configuration cache and said comparator, said memory interface selecting a set of memory access parameters by
• if said received address matches said address range of any one of said memory configuration cache entries, then selecting said set of memory access parameters corresponding to said matching one of said plurality of address ranges,
• if said received address fails to match said address range of any of said memory configuration cache entries, then
• signalling an address range miss,
• outputting said received address,
• receiving a memory configuration cache entry including an address range encompassing said received address and a corresponding set of memory access parameters,
• storing said memory configuration cache entry,
• selecting said set of memory access parameters of said received memory configuration cache entry, and
• said memory interface further providing a memory access cycle corresponding to said selected set of memory access parameters.

A digital data processing system comprising:

• a system bus for transmitting data and addresses;
• a plurality of memories, each memory connected to said system bus for memory access, each memory responsive to a predetermined range of addresses and requiring a predetermined set of memory access parameters;
• a memory configuration cache service unit connected to said system bus, said memory configuration cache service unit storing said predetermined address range and said predetermined set of memory access parameters for each of said plurality of memories, said memory configuration cache service unit supplying on said system bus said predetermined address range and said predetermined set of memory access parameters corresponding to a one of said plurality of memories encompassing a particular memory address received from said system bus during a memory configuration cycle;
• a data processor including
• a memory address generator for generating an address for access to one of said plurality of memories,
• a memory configuration cache having a predetermined plurality of memory configuration cache entries, each memory configuration cache entry including an address range and a corresponding set of memory access parameters;
• a comparator connected to said memory address generator and said memory configuration cache comparing said address to said address range of each of said memory configuration cache entries;
• a memory interface connected to said memory configuration cache and said comparator, said memory interface selecting a set of memory access parameters by
• if said received address matches said address range of any one of said memory configuration cache entries, then selecting said set of memory access parameters corresponding to said matching one of said plurality of address ranges,
• if said received address fails to match said address range of any of said memory configuration cache entries, then
• signalling a memory configuration cycle,
• outputting said received address,
• receiving a memory configuration cache entry including an address range encompassing said received address and a corresponding set of memory access parameters from said memory configuration cache service unit,
• storing said memory configuration cache entry,
• selecting said set of memory access parameters of said received memory configuration cache entry, and
• said memory interface further providing a memory access cycle corresponding to said selected set of memory access parameters.