System and method for converting read cycles into write cycles for improved system performance

A system which performs more efficient data transfer operations, comprising:

• a first bus;
• a second bus;
• bus interface logic coupled between said first bus and said second bus, wherein the bus interface logic includes a write posting buffer;
• a memory coupled to the first bus storing data;
• a first direct memory access transfer device coupled to the first bus;
• a requestor device coupled to the second bus which is operable to initiate a read request to obtain data from the memory coupled to said first bus;
• logic coupled to said requestor device which is operable to create and store a data transfer packet comprising information regarding a desired transfer of data from said memory, wherein said logic operates in response to said read request from the requestor device;
• wherein said direct memory access device is operable to receive said address of said data transfer packet, read said data transfer packet to obtain information regarding said desired data transfer, configure said direct memory access device according to said information regarding said desired transfer in said data transfer packet, and transfer said data from the memory to the requestor device using write cycles;
• wherein said direct memory access device transfers said desired data from the memory to the requestor device using write cycles in response to said read request.

An instrumentation system which performs more efficient data transfer operations, comprising:

• a first bus;
• first bus interface logic coupled to said first bus which includes write posting buffers, a VXI bus;
• second bus interface logic coupled between said first bus and said VXI bus which includes write posting buffers;
• a memory coupled to the computer system bus storing data;
• a direct memory access transfer device coupled to the computer system bus;
• a requestor device coupled to the VXI bus which is operable to initiate a read request to obtain data from the memory coupled to said first bus;
• logic coupled to said requestor device which is operable to create and store a data transfer packet comprising information regarding a desired transfer of data from said memory, wherein said logic operates in response to said read request from the requestor device;
• wherein said direct memory access device is operable to receive said address of said data transfer packet, read said data transfer packet to obtain information regarding said desired data transfer, configure said direct memory access device according to said informational regarding said desired transfer in said data transfer packet, and transfer said data from the memory to the requestor device using write cycles;
• wherein said direct memory access device transfers said desired data from the memory to the requestor device using write cycles in response to said read request.

An instrumentation system which performs more efficient data transfer operations, comprising:

• a computer system including a computer system bus;
• a MXI bus;
• first bus interface logic coupled between said computer system bus and said MXI bus which includes write posting buffers,
• a VXI bus;
• second bus interface logic coupled between said MXI bus and said VXI bus which includes write posting buffers;
• a VXI instrument coupled to the VXI bus storing data;
• a direct memory access transfer device coupled to the computer system bus;
• wherein the computer system desires to read data from the memory comprised in said VXI instrument, wherein the computer system includes:
• means for creating a data transfer packet comprising information regarding a desired transfer of data from said memory in said VXI instrument;
• and
• means for writing an address of said data transfer packet to said direct memory access transfer device;
• wherein said direct memory access device comprises:
• means for reading said data transfer packet to obtain information regarding said desired data transfer;
• and
• means for transferring said desired data from the memory in said VXI instrument to the computer system using write cycles;
• wherein said direct memory access device transfers said desired data from the memory in said VXI instrument to the computer system using write cycles in response to the computer system desiring to read data from the memory comprised in said VXI instrument.

A method for performing data transfers in a system comprising first and second connected buses, wherein a memory is coupled to the first bus storing data, a direct memory access transfer device is coupled to the first bus, and a requestor device is coupled to the second bus which desires to obtain data from the memory coupled to the first bus, the method comprising:

• the requestor device Initiating a read request to read data from the memory;
• creating a data transfer packet comprising information regarding a desired transfer of the data desired to be obtained from the memory;
• storing the packet in a memory;
• writing the address of said data transfer packet to the direct memory access transfer device;
• wherein said creating the data transfer packet, storing the packet in a memory, and writing the address of said data transfer packet to the direct memory access transfer device are performed in response to the requestor devise initiating the read request;
• the direct memory access device reading said data transfer packet to obtain information regarding said desired data transfer;
• the direct memory access device configuring itself based on said data transfer packet, wherein the direct memory access device configures itself to transfer the data from the memory coupled to the first bus to the requestor device using write cycles;
• and
• the direct memory access device transferring the data from the memory coupled to the first bus to the requestor device using write cycles in response to said configuring;
• wherein said creating the data transfer packet, storing the packet in a memory, writing the address of said data transfer packet to the direct memory access transfer device, the direct memory access device reading said data transfer packet, the direct memory access device configuring itself, and the direct memory access device transferring the data using write cycles operates to convert the read request into a write transfer.