Communication apparatus for performing data transfer utilizing direct memory access controller
AssigneeCanon Kabushiki Kaisha
InventorFumio Shoji
Life of this patent
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Abstract
A direct memory access controller (DMAC) comprises a chain DMA mode (which does not require a predetermined software process) and a normal DMA mode (which requires a predetermined software process). When a communication apparatus is in a normal-reception state, data is received utilizing the chain DMA mode and when the apparatus is in a reception-busy state, data is received utilizing the normal DMA mode. By virtue of this feature, in a normal data reception, a memory designated as a DMA transfer destination is switched without delay which will be caused by a software process, thereby preventing overflows of received data due to overhead required by a CPU.
Claims6
A communication apparatus for performing data transfer utilizing a direct memory access controller (DMAC), comprising:
- means for setting a first transfer mode in which a memory associated with data transfer utilizing said DMAC is switched to a memory designated as a next transfer destination, without performing a predetermined software process;
- means for setting a second transfer mode in which a memory associated with data transfer utilizing said DMAC is switched to a memory designated as a next transfer destination, by performing a predetermined software process;
- judging means for judging whether the communication apparatus is in a normal-reception state or a reception-busy state;
- and
- controlling means for controlling data transfer such that if it is judged by said judging means that the communication apparatus is in said normal-reception state, data transfer is performed in said first transfer mode, and if the communication apparatus is in said reception-busy state, data transfer is performed in said second transfer mode.
A communication method of transferring received data utilizing a DMAC, having a first transfer mode in which a memory associated with data transfer utilizing a DMAC is switched to a memory designated as a next transfer destination, without performing a predetermined software process, and a second transfer mode in which a memory associated with data transfer utilizing the DMAC is switched to a memory designated as a next transfer destination, by performing the predetermined software process, comprising the step of:
- judging whether or not data reception process is in a busy-state,
- performing data transfer in said first transfer mode, if said reception process is not in a busy-state;
- and
- performing data transfer in said second transfer mode, if said reception process is in a busy-state.
Dependencies are inferred from the claim text.