Processor and method for out-of-order completion of floating-point operations during load/store multiple operations

A microprocessor capable of completing floating-point instructions out-of-order from a previous load/store multiple instruction, and being connected to a memory, comprising:

• a plurality of general purpose registers for selectively storing integer data;
• a plurality of floating-point registers for selectively storing floating-point data;
• a load/store execution unit that executes load multiple and store multiple instructions which load or store data to or from the plurality of general purpose registers;
• a floating-point execution unit for performing floating-point operations on operand data stored in the plurality of floating point registers;
• a dispatch unit that dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit, wherein the dispatch unit dispatches a multi-register instruction to the load/store unit to begin execution of the multi-register instruction, and wherein, prior to the multi-register instruction finishing execution in the load/store unit, the dispatch unit dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating point registers of the plurality of floating point registers, to the floating point execution unit;
• and
• a completion unit that completes execution of the dispatched floating-point instruction prior to the multi-register instruction finishing execution by causing result data of said floating-point instruction to be stored in at least one of said plurality of floating-point registers.