Personal computer apparatus and method for monitoring memory locations states for facilitating debugging of post and BIOS code

A method of communicating between a computer system and a communications device external to the computer system, the computer system having (i) a central processing unit (CPU) having registers associated therewith and capable of executing code including an operating system, (ii) a programmable read-only memory (PROM) in circuit communication with the CPU and containing code (PROM code) executable on the CPU, (iii) a random access memory (RAM) in circuit communication with the CPU, (iv) a memory controller in circuit communication with the CPU and configured to interface between the CPU and the RAM, (v) a video controller in circuit communication with the CPU and configured to generate signals corresponding to a visual image corresponding to data within a video memory, (vi) a communications controller in circuit communication with the CPU and configured to interface between the CPU and a communications bus, and (vii) a keyboard controller in circuit communication with the CPU and configured to interface between the CPU and a keyboard, comprising the steps of:

• initializing the communications controller to provide a communications link between the external communications device and the computer system;
• starting execution of a PROM code monitor and debugger module;
• transmitting a first monitor command to the monitor and debugger module from the external communications device via the communications link;
• responding to the first monitor command by transmitting to the external communications device from the monitor and debugger module via the communications link a signal corresponding to the then current state of the registers of the CPU;
• transmitting a second monitor command to the monitor and debugger module from the external communications device via the communications link;
• responding to the second monitor command by modifying the current state of the registers of the CPU;
• transmitting a third monitor command to the monitor and debugger module from the external communications device via the communications link;
• responding to the third monitor command by transmitting to the external communications device from the monitor and debugger module via the communications link a signal corresponding to the then current state of at least one memory location;
• transmitting a fourth monitor command to the monitor and debugger module from the external communications device via the communications link;
• responding to the fourth monitor command by modifying the state of at least one memory location;
• transmitting a first debugger command to the monitor and debugger module from the external communications device via the communications link;
• responding to the first debugger command by setting at least one breakpoint corresponding to at least one particular location in the RAM;
• transmitting a second debugger command to the monitor and debugger module from the external communications device via the communications link;
• responding to the second debugger command by clearing at least one breakpoint corresponding to at least one particular location in the RAM;
• transmitting a third debugger command to the monitor and debugger module from the external communications device via the communications link;
• responding to the third debugger command by starting the execution of PROM code by the CPU at a particular code instruction;
• responding to the executing PROM code accessing a portion of the RAM corresponding to a breakpoint by ceasing the execution of PROM code by the CPU;
• responding to the executing PROM code executing from a portion of the RAM corresponding to a breakpoint by ceasing the execution of code by the CPU,
• transmitting a fourth debugger command to the monitor and debugger module from the external communications device via the communications link;
• and
• responding to the fourth debugger command by causing the CPU to execute a single code instruction and transmitting to the external communications device via the communications link a signal corresponding to the then current state of the registers of the CPU.